From: Sekhar Nori Date: Wed, 9 Aug 2017 14:02:47 +0000 (+0530) Subject: ARM: dts: dra71-evm: workaround incorrect DP83867 RX_CTRL pin strap X-Git-Tag: v4.14-rc1~68^2~2^2~3^2~1 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=c17133e086994b3626cc373de8ca22cd8d293a0c;p=linux.git ARM: dts: dra71-evm: workaround incorrect DP83867 RX_CTRL pin strap The DRA71 EVM straps the DP83867 GigaBit Ethernet phy's RX_DV/RX_CTRL pin in mode 1. Unfortunately, the phy data manual disallows this. Add "ti,dp83867-rxctrl-strap-quirk" property to the phy's device-tree node to allow kernel to enable software workaround for this incorrect strap setting. This is as suggested by the phy's datamanual and ensures proper operation of this PHY. This needs to be done for both instances of this PHY present on the board. Signed-off-by: Sekhar Nori Reviewed-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index a6298eb56978..9897e8fa6845 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -191,6 +191,7 @@ dp83867_0: ethernet-phy@2 { ti,tx-internal-delay = ; ti,fifo-depth = ; ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; }; dp83867_1: ethernet-phy@3 { @@ -199,6 +200,7 @@ dp83867_1: ethernet-phy@3 { ti,tx-internal-delay = ; ti,fifo-depth = ; ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; }; };