From: Aaron Brice Date: Fri, 3 Apr 2015 20:39:30 +0000 (-0700) Subject: spi: fsl-dspi: Add cs-sck delays X-Git-Tag: v4.1-rc1~163^2~3^3~2 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=c1c14957afd3026dcbc2e7ca599e6d035c7d8e01;p=linux.git spi: fsl-dspi: Add cs-sck delays Adding fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay properties to support delays before and after starting the clock in a transfer. Signed-off-by: Aaron Brice Signed-off-by: Mark Brown --- diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt index cbbe16ed3874..70af78a9185e 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt @@ -16,6 +16,12 @@ Optional property: in big endian mode, otherwise in native mode(same with CPU), for more detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. +Optional SPI slave node properties: +- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip + select and the start of clock signal, at the start of a transfer. +- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock + signal and deactivating chip select, at the end of a transfer. + Example: dspi0@4002c000 { @@ -43,6 +49,8 @@ dspi0@4002c000 { reg = <0>; linux,modalias = "m25p80"; modal = "at26df081a"; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <50>; }; };