From: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Date: Wed, 10 Dec 2014 02:30:27 +0000 (+0900)
Subject: ARM: shmobile: lager: Fix QSPI mode of SPI-Flash into mode3
X-Git-Tag: v4.0-rc1~69^2~39^2~15
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=cbf41168339adcb48de6a3537f88d4e85285db99;p=linux.git

ARM: shmobile: lager: Fix QSPI mode of SPI-Flash into mode3

In order to change into mode3, CPOL and CPHA bit of SPCMD register
of QSPI is changed. Mode3 can avoid intermediate voltage.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
[horms: Updated changelog and re-ordered properties]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
---

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 636d53bb87a2..bc257e8b1bf2 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -397,6 +397,8 @@ flash: flash@0 {
 		spi-max-frequency = <30000000>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
+		spi-cpha;
+		spi-cpol;
 		m25p,fast-read;
 
 		partition@0 {