From: Bjorn Helgaas <bhelgaas@google.com>
Date: Wed, 1 Oct 2014 18:30:58 +0000 (-0600)
Subject: Merge branches 'pci/aer' and 'pci/virtualization' into next
X-Git-Tag: v3.18-rc1~110^2~6
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=cc0cb67adb97793e76bf6f1f6e05694f6311cebd;p=linux.git

Merge branches 'pci/aer' and 'pci/virtualization' into next

* pci/aer:
  PCI/AER: Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND
  PCI/AER: Add additional PCIe AER error strings
  trace, RAS: Add additional PCIe AER error strings
  trace, RAS: Replace bare numbers with #defines for PCIe AER error strings

* pci/virtualization:
  PCI: Add ACS quirk for Intel 10G NICs
---

cc0cb67adb97793e76bf6f1f6e05694f6311cebd
diff --cc drivers/pci/quirks.c
index 95239e0cfee6,80c2d014283d,322d577503bd..b6c65009e858
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@@@ -3635,21 -3664,6 -3615,23 +3635,23 @@@@ static int pci_quirk_intel_pch_acs(stru
   	return acs_flags & ~flags ? 0 : 1;
   }
   
-  static int pci_quirk_solarflare_acs(struct pci_dev *dev, u16 acs_flags)
++ static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
 + {
 + 	/*
 + 	 * SV, TB, and UF are not relevant to multifunction endpoints.
 + 	 *
-  	 * Solarflare indicates that peer-to-peer between functions is not
-  	 * possible, therefore RR, CR, and DT are not implemented.  Mask
-  	 * these out as if they were clear in the ACS capabilities register.
++ 	 * Multifunction devices are only required to implement RR, CR, and DT
++ 	 * in their ACS capability if they support peer-to-peer transactions.
++ 	 * Devices matching this quirk have been verified by the vendor to not
++ 	 * perform peer-to-peer with other functions, allowing us to mask out
++ 	 * these bits as if they were unimplemented in the ACS capability.
 + 	 */
 + 	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
 + 		       PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
 + 
 + 	return acs_flags ? 0 : 1;
 + }
 + 
   static const struct pci_dev_acs_enabled {
   	u16 vendor;
   	u16 device;
@@@@ -3661,8 -3675,6 -3643,28 +3663,28 @@@@
   	{ PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
   	{ PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
   	{ PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
-  	{ PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_solarflare_acs },
-  	{ PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_solarflare_acs },
++ 	{ PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
++ 	{ PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
   	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
   	{ 0 }
   };