From: Thor Thayer <thor.thayer@linux.intel.com>
Date: Tue, 25 Sep 2018 15:21:10 +0000 (-0500)
Subject: ARM: dts: socfpga: Fix SDRAM node address for Arria10
X-Git-Tag: v4.20-rc1~66^2^2~3
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=ce3bf934f919a7d675c5b7fa4cc233ded9c6256e;p=linux.git

ARM: dts: socfpga: Fix SDRAM node address for Arria10

The address in the SDRAM node was incorrect. Fix this to agree with the
correct address and to match the reg definition block.

Cc: stable@vger.kernel.org
Fixes: 54b4a8f57848b("arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS support")
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 4e0c26423d84..59ef13e37536 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -628,7 +628,7 @@ spi1: spi@ffda5000 {
 			status = "disabled";
 		};
 
-		sdr: sdr@ffc25000 {
+		sdr: sdr@ffcfb100 {
 			compatible = "altr,sdr-ctl", "syscon";
 			reg = <0xffcfb100 0x80>;
 		};