From: Hans de Goede Date: Sat, 19 Sep 2015 21:56:44 +0000 (-0400) Subject: pinctrl: sun5i: Fix a10s pwm1 pinctrl mapping X-Git-Tag: v4.3-rc6~13^2~2 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=d50a9e1b6de45db883f594cea0ecd1379fd3f669;p=linux.git pinctrl: sun5i: Fix a10s pwm1 pinctrl mapping The comment for PG14 mux setting 3 already correctly states that this muxes PG13 to pwm1, but the text ascociated with it said uart3, fix this. Note that we use "pwm" rather then "pwm1" to be consistent with pwm0 where the mux setting is also simply called "pwm" and to be consistent with sun4i/sun7i which do the same. Signed-off-by: Hans de Goede Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c index 63676617bc59..f9a3f8f446f7 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c @@ -653,7 +653,7 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ - SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */ + SUNXI_FUNCTION(0x3, "pwm"), /* PWM1 */ SUNXI_FUNCTION(0x5, "uart2"), /* CTS */ SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ };