From: Icenowy Zheng Date: Sat, 25 Mar 2017 14:50:09 +0000 (+0800) Subject: phy: sun4i-usb: change PHYCTL register clearing code X-Git-Tag: v4.12-rc1~97^2~26^2~28 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=d699c1d0860aa8b3031d56ec861e6c2f2e37df95;p=linux.git phy: sun4i-usb: change PHYCTL register clearing code It seems that all SoCs with the PHYCTL register offset as 0x10 need the PHYCTL register to be cleared before it's written. Change PHYCTL register clearing code to judge whether clearing is needed based on the PHYCTL offset. Signed-off-by: Icenowy Zheng Signed-off-by: Kishon Vijay Abraham I --- diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c index a21b5f24a340..62b4d25448c6 100644 --- a/drivers/phy/phy-sun4i-usb.c +++ b/drivers/phy/phy-sun4i-usb.c @@ -188,10 +188,8 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data, spin_lock_irqsave(&phy_data->reg_lock, flags); - if (phy_data->cfg->type == sun8i_a33_phy || - phy_data->cfg->type == sun50i_a64_phy || - phy_data->cfg->type == sun8i_v3s_phy) { - /* A33 or A64 needs us to set phyctl to 0 explicitly */ + if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) { + /* SoCs newer than A33 need us to set phyctl to 0 explicitly */ writel(0, phyctl); }