From: Dave Airlie <airlied@redhat.com>
Date: Wed, 18 Dec 2013 00:39:56 +0000 (+1000)
Subject: Merge tag 'drm-intel-next-2013-11-29' of git://people.freedesktop.org/~danvet/drm... 
X-Git-Tag: v3.14-rc1~47^2~90
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=da32cc90cbc865c6b49bdc2e0d81b2df3972e5ec;p=linux.git

Merge tag 'drm-intel-next-2013-11-29' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

- some more ppgtt prep patches from Ben
- a few fbc fixes from Ville
- power well rework from Imre
- vlv forcewake improvements from Deepak S, Ville and Jesse
- a few smaller things all over

[airlied: fixup forwcewake conflict]
* tag 'drm-intel-next-2013-11-29' of git://people.freedesktop.org/~danvet/drm-intel: (97 commits)
  drm/i915: Fix port name in vlv_wait_port_ready() timeout warning
  drm/i915: Return a drm_mode_status enum in the mode_valid vfuncs
  drm/i915: add intel_display_power_enabled_sw() for use in atomic ctx
  drm/i915: drop DRM_ERROR in intel_fbdev init
  drm/i915/vlv: use parallel context restore when coming out of RC6
  drm/i915/vlv: use a lower RC6 timeout on VLV
  drm/i915/sdvo: Fix up debug output to not split lines
  drm/i915: make sparse happy for the new vlv mmio read function
  drm/i915: drop the right force-wake engine in the vlv mmio funcs
  drm/i915: Fix GT wake FIFO free entries for VLV
  drm/i915: Report all GTFIFODBG errors
  drm/i915: Enabling DebugFS for valleyview forcewake counts
  drm/i915/vlv: Valleyview support for forcewake Individual power wells.
  drm/i915: Add power well arguments to force wake routines.
  drm/i915: Do not attempt to re-enable an unconnected primary plane
  drm/i915: add a debugfs entry for power domain info
  drm/i915: add a default always-on power well
  drm/i915: don't do BDW/HSW specific powerdomains init on other platforms
  drm/i915: protect HSW power well check with IS_HASWELL in redisable_vga
  drm/i915: use IS_HASWELL/BROADWELL instead of HAS_POWER_WELL
  ...

Conflicts:
	drivers/gpu/drm/i915/intel_display.c
---

da32cc90cbc865c6b49bdc2e0d81b2df3972e5ec
diff --cc drivers/gpu/drm/i915/i915_drv.h
index ccdbecca070d,64ed8f4d991f..780f815b6c9f
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -1813,10 -1840,8 +1840,9 @@@ struct drm_i915_file_private 
  #define HAS_IPS(dev)		(IS_ULT(dev) || IS_BROADWELL(dev))
  
  #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
- #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev) || IS_BROADWELL(dev))
  #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
  #define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))
 +#define HAS_PC8(dev)		(IS_HASWELL(dev)) /* XXX HSW:ULX */
  
  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
diff --cc drivers/gpu/drm/i915/intel_display.c
index 080f6fd4e839,0332d7ca892d..0bb3d6d596d9
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -6402,7 -6583,7 +6583,7 @@@ static void hsw_restore_lcpll(struct dr
  
  	/* Make sure we're not on PC8 state before disabling PC8, otherwise
  	 * we'll hang the machine! */
- 	gen6_gt_force_wake_get(dev_priv);
 -	dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
++	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
  
  	if (val & LCPLL_POWER_DOWN_ALLOW) {
  		val &= ~LCPLL_POWER_DOWN_ALLOW;
@@@ -6436,7 -6617,7 +6617,7 @@@
  			DRM_ERROR("Switching back to LCPLL failed\n");
  	}
  
- 	gen6_gt_force_wake_put(dev_priv);
 -	dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
++	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
  }
  
  void hsw_enable_pc8_work(struct work_struct *__work)