From: Peter Griffin Date: Wed, 10 Jun 2015 14:04:00 +0000 (+0200) Subject: ARM: STi: DT: Add STiH407 family tsin5 pinctrl configuration X-Git-Tag: v4.3-rc1~120^2~45^2~9 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=dd72896f0d7cbbda0b404ed4b8ad46b56f363fc4;p=linux.git ARM: STi: DT: Add STiH407 family tsin5 pinctrl configuration tsin5 can only be configured for serial data transfer. However depending on board design, two alternate tsin5 pin configurations are available, both in pin-controller-front0. pinctrl_tsin5_serial_alt1 is brought out on B2120 reference design as TSD on NIMB slot of the B2004A daughter board. Signed-off-by: Peter Griffin Signed-off-by: Maxime Coquelin --- diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 50b5bed50d21..f513a29fbf33 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -547,6 +547,27 @@ st,pins { }; }; }; + + tsin5 { + pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { + st,pins { + DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { + st,pins { + DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; }; pin-controller-front1 {