From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Date: Thu, 23 Nov 2017 10:58:50 +0000 (+0100)
Subject: arm64: dts: renesas: r8a7795: Increase the number of GPIO bank 1 ports to 29
X-Git-Tag: v4.16-rc1~100^2~59^2~12
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=eb14ed1ad7b6750b6b82e7f556f2c1c340f35b8f;p=linux.git

arm64: dts: renesas: r8a7795: Increase the number of GPIO bank 1 ports to 29

This patch changes the number of GPIO bank 1 ports to 29 because GP-1-28
port pin of R8A7795 ES2.0 SoC support was added.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 291e0c4994d0813f ("arm64: dts: r8a7795: Add support for R-Car H3 ES2.0")
[geert: Keep 28 GPIOs on H3 ES1.x after r8a7795.dtsi sharing]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 29b52d89c78a..26769a11a190 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -109,6 +109,10 @@ fdp1@fe948000 {
 	};
 };
 
+&gpio1 {
+	gpio-ranges = <&pfc 0 32 28>;
+};
+
 &ipmmu_vi0 {
 	renesas,ipmmu-main = <&ipmmu_mm 11>;
 };
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index a438d58f1b50..6db4f10376a1 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -240,7 +240,7 @@ gpio1: gpio@e6051000 {
 			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 			#gpio-cells = <2>;
 			gpio-controller;
-			gpio-ranges = <&pfc 0 32 28>;
+			gpio-ranges = <&pfc 0 32 29>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			clocks = <&cpg CPG_MOD 911>;