From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Tue, 17 May 2016 17:27:29 +0000 (-0700)
Subject: Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git... 
X-Git-Tag: v4.7-rc1~165
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=ede40902cf80714ece199977b308e2ee437cae0b;p=linux.git

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq updates from Thomas Gleixner:
 "This update delivers:

   - Yet another interrupt chip diver (LPC32xx)
   - Core functions to handle partitioned per-cpu interrupts
   - Enhancements to the IPI core
   - Proper handling of irq type configuration
   - A large set of ARM GIC enhancements
   - The usual pile of small fixes, cleanups and enhancements"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (31 commits)
  irqchip/bcm2836: Use a more generic memory barrier call
  irqchip/bcm2836: Fix compiler warning on 64-bit build
  irqchip/bcm2836: Drop smp_set_ops on arm64 builds
  irqchip/gic: Add helper functions for GIC setup and teardown
  irqchip/gic: Store GIC configuration parameters
  irqchip/gic: Pass GIC pointer to save/restore functions
  irqchip/gic: Return an error if GIC initialisation fails
  irqchip/gic: Remove static irq_chip definition for eoimode1
  irqchip/gic: Don't initialise chip if mapping IO space fails
  irqchip/gic: WARN if setting the interrupt type for a PPI fails
  irqchip/gic: Don't unnecessarily write the IRQ configuration
  irqchip: Mask the non-type/sense bits when translating an IRQ
  genirq: Ensure IRQ descriptor is valid when setting-up the IRQ
  irqchip/gic-v3: Configure all interrupts as non-secure Group-1
  irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratum
  irqchip/irq-alpine-msi: Don't use <asm-generic/msi.h>
  irqchip/mbigen: Checking for IS_ERR() instead of NULL
  irqchip/gic-v3: Remove inexistant register definition
  irqchip/gicv3-its: Don't allow devices whose ID is outside range
  irqchip: Add LPC32xx interrupt controller driver
  ...
---

ede40902cf80714ece199977b308e2ee437cae0b
diff --cc drivers/irqchip/irq-gic.c
index 095bb5b5c3f2,113e2d02c812..1de20e14a721
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@@ -489,8 -486,9 +486,10 @@@ static int gic_cpu_init(struct gic_chip
  		/*
  		 * Get what the GIC says our CPU mask is.
  		 */
- 		BUG_ON(cpu >= NR_GIC_CPU_IF);
+ 		if (WARN_ON(cpu >= NR_GIC_CPU_IF))
+ 			return -EINVAL;
+ 
 +		gic_check_cpu_features();
  		cpu_mask = gic_get_cpumask(gic);
  		gic_cpu_map[cpu] = cpu_mask;
  
@@@ -1012,24 -1029,28 +1030,26 @@@ static const struct irq_domain_ops gic_
  	.unmap = gic_irq_domain_unmap,
  };
  
- static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
- 			   void __iomem *dist_base, void __iomem *cpu_base,
- 			   u32 percpu_offset, struct fwnode_handle *handle)
+ static int __init __gic_init_bases(struct gic_chip_data *gic, int irq_start,
+ 				   struct fwnode_handle *handle)
  {
  	irq_hw_number_t hwirq_base;
- 	struct gic_chip_data *gic;
- 	int gic_irqs, irq_base, i;
- 
- 	BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
+ 	int gic_irqs, irq_base, i, ret;
  
- 	gic = &gic_data[gic_nr];
+ 	if (WARN_ON(!gic || gic->domain))
+ 		return -EINVAL;
  
 -	gic_check_cpu_features();
 -
  	/* Initialize irq_chip */
- 	if (static_key_true(&supports_deactivate) && gic_nr == 0) {
- 		gic->chip = gic_eoimode1_chip;
+ 	gic->chip = gic_chip;
+ 
+ 	if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) {
+ 		gic->chip.irq_mask = gic_eoimode1_mask_irq;
+ 		gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
+ 		gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
+ 		gic->chip.name = kasprintf(GFP_KERNEL, "GICv2");
  	} else {
- 		gic->chip = gic_chip;
- 		gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr);
+ 		gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d",
+ 					   (int)(gic - &gic_data[0]));
  	}
  
  #ifdef CONFIG_SMP