From: Arnd Bergmann Date: Mon, 31 Oct 2011 22:42:23 +0000 (+0100) Subject: Merge branch 'stericsson/cleanup' into next/timer X-Git-Tag: v3.2-rc1~96^2 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=eed1e576507b52e03e549e0c9e0c747978122403;p=linux.git Merge branch 'stericsson/cleanup' into next/timer The timer and cleanup branches from stericsson conflict, so I'm merging them here. Conflicts: arch/arm/mach-ux500/Makefile arch/arm/mach-ux500/cpu.c Signed-off-by: Arnd Bergmann --- eed1e576507b52e03e549e0c9e0c747978122403 diff --cc arch/arm/mach-ux500/Makefile index be915a1ac404,9fd00a6d4248..6bd2f451c185 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@@ -3,7 -3,8 +3,8 @@@ # obj-y := clock.o cpu.o devices.o devices-common.o \ - id.o usb.o + id.o usb.o timer.o + obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \ diff --cc arch/arm/mach-ux500/cpu.c index 797f3642fc30,252e8b3c5706..1405d0eb7edb --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@@ -10,10 -10,7 +10,8 @@@ #include #include #include +#include - #include - #include #include #include #include @@@ -56,66 -50,30 +50,3 @@@ void __init ux500_init_irq(void prcmu_early_init(); clk_init(); } - - #ifdef CONFIG_CACHE_L2X0 - static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask) - { - /* wait for the operation to complete */ - while (readl_relaxed(reg) & mask) - ; - } - - static inline void ux500_cache_sync(void) - { - void __iomem *base = l2x0_base; - - writel_relaxed(0, base + L2X0_CACHE_SYNC); - ux500_cache_wait(base + L2X0_CACHE_SYNC, 1); - } - - /* - * The L2 cache cannot be turned off in the non-secure world. - * Dummy until a secure service is in place. - */ - static void ux500_l2x0_disable(void) - { - } - - /* - * This is only called when doing a kexec, just after turning off the L2 - * and L1 cache, and it is surrounded by a spinlock in the generic version. - * However, we're not really turning off the L2 cache right now and the - * PL310 does not support exclusive accesses (used to implement the spinlock). - * So, the invalidation needs to be done without the spinlock. - */ - static void ux500_l2x0_inv_all(void) - { - void __iomem *base = l2x0_base; - uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */ - - /* invalidate all ways */ - writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY); - ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask); - ux500_cache_sync(); - } -- - static int ux500_l2x0_init(void) -static void __init ux500_timer_init(void) --{ -#ifdef CONFIG_LOCAL_TIMERS - /* Setup the local timer base */ -- if (cpu_is_u5500()) - l2x0_base = __io_address(U5500_L2CC_BASE); - twd_base = __io_address(U5500_TWD_BASE); -- else if (cpu_is_u8500()) - l2x0_base = __io_address(U8500_L2CC_BASE); - twd_base = __io_address(U8500_TWD_BASE); -- else -- ux500_unknown_soc(); - - /* 64KB way size, 8 way associativity, force WA */ - l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); - - /* Override invalidate function */ - outer_cache.disable = ux500_l2x0_disable; - outer_cache.inv_all = ux500_l2x0_inv_all; -#endif - if (cpu_is_u5500()) - mtu_base = __io_address(U5500_MTU0_BASE); - else if (cpu_is_u8500ed()) - mtu_base = __io_address(U8500_MTU0_BASE_ED); - else if (cpu_is_u8500()) - mtu_base = __io_address(U8500_MTU0_BASE); - else - ux500_unknown_soc(); -- - return 0; - nmdk_timer_init(); --} - early_initcall(ux500_l2x0_init); - #endif - -struct sys_timer ux500_timer = { - .init = ux500_timer_init, -};