From: Ondrej Jirman Date: Tue, 4 Jun 2019 15:40:36 +0000 (+0200) Subject: clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register X-Git-Tag: v5.3-rc1~59^2~4^5~2^2~1 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=f167675486c37b88620d344fbb12d06e34f11d47;p=linux.git clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register The current code defines W1 clock gate to be at 0x1cc, overlaying it with the IR gate. Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver causing interrupt floods on H6 (because interrupt flags can't be cleared, due to IR module's bus being disabled). Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU") Signed-off-by: Ondrej Jirman Acked-by: Clément Péron Signed-off-by: Maxime Ripard --- diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c index 27554eaf6929..8d05d4f1f8a1 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2", static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1", 0x1cc, BIT(0), 0); static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1", - 0x1cc, BIT(0), 0); + 0x1ec, BIT(0), 0); /* Information of IR(RX) mod clock is gathered from BSP source code */ static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };