From: David Francis Date: Fri, 9 Nov 2018 16:50:18 +0000 (-0500) Subject: drm/amd/display: Allow clock lower on dce100 X-Git-Tag: v5.0-rc1~185^2~4^2~47 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=fa3547dd92deff8624a18621035e876f94f24a1b;p=linux.git drm/amd/display: Allow clock lower on dce100 dce100 was set to always pass safe_to_lower = false to the clock manager Thus, on suspend the clocks were not being set to 0 which is incorrect behaviour This was causing s3 resume to blackscreen on intel CPUs with dce100 GPUs attached (Note that the hash in this Fixes: tag is the hash on Alex's tree) Fixes: ae7d8aeb38d7 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead") Signed-off-by: David Francis Reviewed-by: Harry Wentland Acked-by: Leo Li Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index bc50a8e25f4f..87771676acac 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -117,6 +117,18 @@ void dce100_prepare_bandwidth( false); } +void dce100_optimize_bandwidth( + struct dc *dc, + struct dc_state *context) +{ + dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); + + dc->res_pool->clk_mgr->funcs->update_clocks( + dc->res_pool->clk_mgr, + context, + true); +} + /**************************************************************************/ void dce100_hw_sequencer_construct(struct dc *dc) @@ -125,6 +137,6 @@ void dce100_hw_sequencer_construct(struct dc *dc) dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; - dc->hwss.optimize_bandwidth = dce100_prepare_bandwidth; + dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; }