Olof Johansson [Thu, 16 Jan 2020 23:45:35 +0000 (15:45 -0800)]
Merge tag 'qcom-drivers-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
Qualcomm driver updates for v5.6
* SCM major refactoring and cleanup
* Properly flag active only power domains as active only
* Add SC7180 and SM8150 RPMH power domains
* Return EPROBE_DEFER from QMI if packet family is not yet available
* tag 'qcom-drivers-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits)
firmware: qcom_scm: Dynamically support SMCCC and legacy conventions
firmware: qcom_scm: Remove thin wrappers
firmware: qcom_scm: Order functions, definitions by service/command
firmware: qcom_scm-32: Add device argument to atomic calls
firmware: qcom_scm-32: Create common legacy atomic call
firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_call
firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls
firmware: qcom_scm-32: Add funcnum IDs
firmware: qcom_scm-32: Use SMC arch wrappers
firmware: qcom_scm-64: Improve SMC convention detection
firmware: qcom_scm-64: Move SMC register filling to qcom_scm_call_smccc
firmware: qcom_scm-64: Add SCM results struct
firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_desc
firmware: qcom_scm-64: Make SMC macros less magical
firmware: qcom_scm: Remove unused qcom_scm_get_version
firmware: qcom_scm: Apply consistent naming scheme to command IDs
firmware: qcom_scm: Rename macros and structures
soc: qcom: rpmhpd: Set 'active_only' for active only power domains
firmware: scm: Add stubs for OCMEM and restore_sec_cfg_available
dt-bindings: power: rpmpd: Convert rpmpd bindings to yaml
...
Olof Johansson [Thu, 16 Jan 2020 20:47:12 +0000 (12:47 -0800)]
Merge tag 'soc-fsl-next-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers
NXP/FSL SoC driver updates for v5.6
QUICC Engine drivers
- Improve the QE drivers to be compatible with ARM/ARM64/PPC64
architectures
- Various cleanups to the QE drivers
* tag 'soc-fsl-next-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux: (49 commits)
soc: fsl: qe: remove set but not used variable 'mm_gc'
soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE
soc: fsl: qe: remove unused #include of asm/irq.h from ucc.c
net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32
net/wan/fsl_ucc_hdlc: reject muram offsets above 64K
net/wan/fsl_ucc_hdlc: fix reading of __be16 registers
net/wan/fsl_ucc_hdlc: avoid use of IS_ERR_VALUE()
soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c
soc: fsl: qe: drop pointless check in qe_sdma_init()
soc: fsl: qe: drop use of IS_ERR_VALUE in qe_sdma_init()
soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c
soc: fsl: qe: refactor cpm_muram_alloc_common to prevent BUG on error path
soc: fsl: qe: drop broken lazy call of cpm_muram_init()
soc: fsl: qe: make cpm_muram_free() ignore a negative offset
soc: fsl: qe: make cpm_muram_free() return void
soc: fsl: qe: change return type of cpm_muram_alloc() to s32
serial: ucc_uart: access __be32 field using be32_to_cpu
serial: ucc_uart: limit brg-frequency workaround to PPC32
serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe()
serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32
...
Olof Johansson [Thu, 16 Jan 2020 18:47:27 +0000 (10:47 -0800)]
Merge tag 'imx-driver-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX driver changes for 5.6:
- Add i.MX8MP SoC driver support.
- Allow IMX DSP Protocol driver to be built as module.
- Add COMPILE_TEST for IMX_SCU_SOC driver to increase build coverage.
- Print SoC type and revision in i.MX8 SoC driver, as this is useful
information to have when looking through boot log.
* tag 'imx-driver-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
firmware: imx: Allow IMX DSP to be selected as module
soc: imx: Enable compile testing of IMX_SCU_SOC
soc: imx: Add i.MX8MP SoC driver support
soc: imx8: print SoC type and revision
Olof Johansson [Thu, 16 Jan 2020 18:45:42 +0000 (10:45 -0800)]
Merge tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu into arm/drivers
mvebu drivers for 5.6 (part 1)
- Various cleanup on the following drivers:
- Turris Mox rWTM firmware
- Moxtet bus
- Armada 37xx rWTM mailbox
- Marvell EBU Device Bus
* tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu:
mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resource
memory: mvebu-devbus: convert to devm_platform_ioremap_resource
bus: moxtet: declare moxtet_bus_type as static
firmware: turris-mox-rwtm: small white space cleanup
Olof Johansson [Thu, 16 Jan 2020 18:42:17 +0000 (10:42 -0800)]
Merge tag 'tegra-for-5.6-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
soc: tegra: Changes for v5.6-rc1
This adds a couple of optimizations to how the chip ID and straps are
read and adds support for the FUSE block on Tegra194. Included is also a
small optimization for the coupled regulator driver to abort early if no
voltage change has occurred.
* tag 'tegra-for-5.6-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: fuse: Unmap registers once they are not needed anymore
soc/tegra: fuse: Correct straps' address for older Tegra124 device trees
soc/tegra: fuse: Warn if straps are not ready
soc/tegra: fuse: Cache values of straps and Chip ID registers
soc/tegra: regulators: Do nothing if voltage is unchanged
soc/tegra: fuse: Add APB DMA dependency for Tegra20
soc/tegra: fuse: Add Tegra194 support
Olof Johansson [Thu, 16 Jan 2020 18:41:47 +0000 (10:41 -0800)]
Merge tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
memory: tegra: Changes for v5.6-rc1
This adds a couple of fixes for the Tegra30 EMC frequency scaling code
and adds support for EMC frequency scaling on Tegra186 and later.
* tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
memory: tegra30-emc: Correct error message for timed out auto calibration
memory: tegra30-emc: Firm up hardware programming sequence
memory: tegra30-emc: Firm up suspend/resume sequence
memory: tegra: Correct reset value of xusb_hostr
memory: tegra: Add support for the Tegra194 memory controller
memory: tegra: Only include support for enabled SoCs
memory: tegra: Support DVFS on Tegra186 and later
memory: tegra: Add system sleep support
memory: tegra: Extract memory client SID programming
memory: tegra: Add per-SoC data for Tegra186
memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186
memory: tegra: Implement EMC debugfs interface on Tegra30
memory: tegra: Implement EMC debugfs interface on Tegra20
memory: tegra: Refashion EMC debugfs interface on Tegra124
Olof Johansson [Sat, 11 Jan 2020 06:27:09 +0000 (22:27 -0800)]
Merge tag 'samsung-drivers-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers
Samsung soc drivers changes for v5.6
1. Convert to managed (devm_x()) versions,
2. Cleanups (Samsung and Exynos names).
* tag 'samsung-drivers-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
memory: samsung: Rename Exynos to lowercase
soc: samsung: Rename Samsung and Exynos to lowercase
memory: samsung: exynos5422-dmc: Convert to devm_platform_ioremap_resource
soc: samsung: exynos-pmu: Convert to devm_platform_ioremap_resource
Olof Johansson [Sat, 11 Jan 2020 06:20:36 +0000 (22:20 -0800)]
Merge tag 'reset-for-5.6' of git://git.pengutronix.de/pza/linux into arm/drivers
Reset controller updates for v5.6
This tag adds support for the Nuvoton NPCM, Intel Gatway SoC, and
Broadcom BCM7216 RESCAL reset controllers, adds missing SCSSI reset
controls for newer Uniphier SoCs, aligns the program flow in the
devm_reset_controller_register, __devm_reset_control_get, and
devm_reset_control_array_get functions for better consistency,
and allows to build the Qcom AOSS reset driver as a module.
This is based on v5.5-rc3 because the core patch depends on commit db23808615e2 ("reset: Do not register resource data for missing
resets").
* tag 'reset-for-5.6' of git://git.pengutronix.de/pza/linux:
reset: qcom-aoss: Allow CONFIG_RESET_QCOM_AOSS to be a tristate
reset: Add Broadcom STB RESCAL reset controller
dt-bindings: reset: Document BCM7216 RESCAL reset controller
reset: intel: Add system reset controller driver
dt-bindings: reset: Add YAML schemas for the Intel Reset controller
reset: uniphier: Add SCSSI reset control for each channel
reset: Align logic and flow in managed helpers
reset: npcm: add NPCM reset controller driver
dt-bindings: reset: Add binding constants for NPCM7xx reset controller
dt-bindings: reset: add NPCM reset controller documentation
Dmitry Osipenko [Wed, 18 Dec 2019 18:23:04 +0000 (21:23 +0300)]
soc/tegra: fuse: Unmap registers once they are not needed anymore
Both Chip ID and strapping registers are now read out during of APB MISC
initialization, the registers' mapping isn't needed anymore once registers
are read. Hence let's unmap registers once they are not needed anymore,
for consistency.
Dmitry Osipenko [Wed, 18 Dec 2019 18:23:03 +0000 (21:23 +0300)]
soc/tegra: fuse: Correct straps' address for older Tegra124 device trees
Trying to read out Chip ID before APBMISC registers are mapped won't
succeed, in a result Tegra124 gets a wrong address for the HW straps
register if machine uses an old outdated device tree.
Dmitry Osipenko [Wed, 18 Dec 2019 18:23:02 +0000 (21:23 +0300)]
soc/tegra: fuse: Warn if straps are not ready
Now both Chip ID and HW straps are becoming available at the same time,
thus we could simply check the availability of the ID in order to check
the availability of the straps. We couldn't check straps for 0x0 because
it could be a correct value.
This change didn't uncover any problems, but anyways it is nicer to have
straps verified for consistency with the Chip ID verification.
Dmitry Osipenko [Fri, 20 Dec 2019 02:08:48 +0000 (05:08 +0300)]
memory: tegra30-emc: Firm up hardware programming sequence
Previously there was a problem where a late handshake handling caused
a memory corruption, this problem was resolved by issuing calibration
command right after changing the timing, but looks like the solution
wasn't entirely correct since calibration interval could be disabled as
well. Now programming sequence is completed immediately after receiving
handshake from CaR, without potentially long delays and in accordance to
the TRM's programming guide.
Secondly, the TRM's programming guide suggests to flush EMC writes by
reading any *MC* register before doing CaR changes. This is also addressed
now.
Dmitry Osipenko [Fri, 20 Dec 2019 02:08:47 +0000 (05:08 +0300)]
memory: tegra30-emc: Firm up suspend/resume sequence
The current code doesn't prevent race conditions of suspend/resume vs CCF.
Let's take exclusive control over the EMC clock during suspend in a way
that is free from race conditions.
Thierry Reding [Sun, 22 Dec 2019 14:10:32 +0000 (15:10 +0100)]
memory: tegra: Add support for the Tegra194 memory controller
The memory and external memory controllers on Tegra194 are very similar
to their predecessors from Tegra186. Add the necessary SoC-specific data
to support the newer versions.
Thierry Reding [Sun, 22 Dec 2019 14:10:30 +0000 (15:10 +0100)]
memory: tegra: Support DVFS on Tegra186 and later
Add a Tegra186 (and later) EMC driver that reads the EMC DVFS tables
from BPMP and uses the EMC clock to change the external memory clock.
This currently only provides a debugfs interface to show the available
frequencies and set lower and upper limits of the allowed range. This
can be used for testing the various frequencies. The goal is to
eventually integrate this with the interconnect framework so that the
EMC frequency can be scaled based on demand from memory clients.
Thierry Reding [Sun, 22 Dec 2019 14:10:29 +0000 (15:10 +0100)]
memory: tegra: Add system sleep support
Add system suspend/resume support for the memory controller found on
Tegra186 and later. This is required so that the SID registers can be
reprogrammed after their content was lost during system sleep.
Thierry Reding [Sun, 22 Dec 2019 11:40:33 +0000 (12:40 +0100)]
memory: tegra: Implement EMC debugfs interface on Tegra30
A common debugfs interface is already available on Tegra20, Tegra124,
Tegra186 and Tegra194. Implement the same interface on Tegra30 to enable
testing of the EMC frequency scaling code using a unified interface.
Thierry Reding [Sun, 22 Dec 2019 11:40:32 +0000 (12:40 +0100)]
memory: tegra: Implement EMC debugfs interface on Tegra20
A common debugfs interface is already available on Tegra124, Tegra186
and Tegra194. Implement the same interface on Tegra20 to enable testing
of the EMC frequency scaling code using a unified interface.
Thierry Reding [Sun, 22 Dec 2019 11:39:17 +0000 (12:39 +0100)]
memory: tegra: Refashion EMC debugfs interface on Tegra124
The current debugfs interface is only partially useful. While it allows
listing supported frequencies and testing individual clock rates, it is
limited in that it can't be used to restrict the range of frequencies
that the driver is allowed to set. This is something we may want to use
to test adaptive scaling once that's implemented.
Daniel Baluta [Sat, 4 Jan 2020 15:39:53 +0000 (15:39 +0000)]
firmware: imx: Allow IMX DSP to be selected as module
IMX DSP is only needed by SOF or any other module that
wants to communicate with the DSP. When SOF is build
as a module IMX DSP is forced to be built inside the
kernel image. This is not optimal, so allow IMX DSP
to be built as a module.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
YueHaibing [Wed, 8 Jan 2020 13:09:26 +0000 (21:09 +0800)]
soc: fsl: qe: remove set but not used variable 'mm_gc'
drivers/soc/fsl/qe/gpio.c: In function qe_pin_request:
drivers/soc/fsl/qe/gpio.c:163:26: warning: variable mm_gc set but not used [-Wunused-but-set-variable]
commit 1e714e54b5ca ("powerpc: qe_lib-gpio: use gpiochip data pointer")
left behind this unused variable.
Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Chen Zhou <chenzhou10@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
Olof Johansson [Wed, 8 Jan 2020 18:26:26 +0000 (10:26 -0800)]
Merge tag 'cpuidle_psci-v5.5-rc4' of git://git.linaro.org/people/ulf.hansson/linux-pm into arm/drivers
Initial support for hierarchical CPU arrangement, managed by PSCI and its
corresponding cpuidle driver. This support is based upon using the generic
PM domain, which already supports devices belonging to CPUs.
Finally, these is a DTS patch that enables the hierarchical topology to be
used for the Qcom 410c Dragonboard, which supports the PSCI OS-initiated
mode.
* tag 'cpuidle_psci-v5.5-rc4' of git://git.linaro.org/people/ulf.hansson/linux-pm: (611 commits)
arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916
cpuidle: psci: Add support for PM domains by using genpd
PM / Domains: Introduce a genpd OF helper that removes a subdomain
cpuidle: psci: Support CPU hotplug for the hierarchical model
cpuidle: psci: Manage runtime PM in the idle path
cpuidle: psci: Prepare to use OS initiated suspend mode via PM domains
cpuidle: psci: Attach CPU devices to their PM domains
cpuidle: psci: Add a helper to attach a CPU to its PM domain
cpuidle: psci: Support hierarchical CPU idle states
cpuidle: psci: Simplify OF parsing of CPU idle state nodes
cpuidle: dt: Support hierarchical CPU idle states
of: base: Add of_get_cpu_state_node() to get idle states for a CPU node
firmware: psci: Export functions to manage the OSI mode
dt: psci: Update DT bindings to support hierarchical PSCI states
cpuidle: psci: Align psci_power_state count with idle state count
Linux 5.5-rc4
locks: print unsigned ino in /proc/locks
riscv: export flush_icache_all to modules
riscv: reject invalid syscalls below -1
riscv: fix compile failure with EXPORT_SYMBOL() & !MMU
...
Dan Carpenter [Wed, 11 Dec 2019 14:47:10 +0000 (15:47 +0100)]
firmware: turris-mox-rwtm: small white space cleanup
This patch deletes a stray tab.
Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Colin King <colin.king@canonical.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Elliot Berman [Tue, 7 Jan 2020 21:04:26 +0000 (13:04 -0800)]
firmware: qcom_scm: Dynamically support SMCCC and legacy conventions
Dynamically support SMCCCC and legacy conventions by detecting which
convention to use at runtime. qcom_scm_call_atomic and qcom_scm_call can
then be moved in qcom_scm.c and use underlying convention backend as
appropriate. Thus, rename qcom_scm-64,-32 to reflect that they are
backends for -smc and -legacy, respectively.
Also add support for making SCM calls earlier than when SCM driver
probes to support use cases such as qcom_scm_set_cold_boot_addr. Support
is added by lazily initializing the convention and guarding the query
with a spin lock. The limitation of these early SCM calls is that they
cannot use DMA, as in the case of >4 arguments for SMC convention and
any non-atomic call for legacy convention.
Elliot Berman [Tue, 7 Jan 2020 21:04:25 +0000 (13:04 -0800)]
firmware: qcom_scm: Remove thin wrappers
qcom_scm-32 and qcom_scm-64 implementations are nearly identical, so
make qcom_scm_call and qcom_scm_call_atomic unique to each and the SCM
descriptor creation common to each. There are the following catches:
- __qcom_scm_is_call_available is still in each -32,-64 implementation
as the argument is unique to each convention
- For some functions, only one implementation was provided in -32 or
-64. The actual implementation was moved into qcom_scm.c
- io_writel and io_readl in -64 were non-atomic calls and in -32 they
were. Atomic is the better option, so use it.
Elliot Berman [Tue, 7 Jan 2020 21:04:24 +0000 (13:04 -0800)]
firmware: qcom_scm: Order functions, definitions by service/command
Definitions throughout qcom_scm are loosely grouped and loosely ordered.
Sort all the functions/definitions by service ID/command ID to improve
sanity when needing to add new functionality to this driver.
Elliot Berman [Tue, 7 Jan 2020 21:04:22 +0000 (13:04 -0800)]
firmware: qcom_scm-32: Create common legacy atomic call
Per [1], legacy calling convention supports up to 5 arguments and 3
return values. Create one function to support this combination, and
remove the original "atomic1" and "atomic2" variants for 1 and 2
arguments. This more closely aligns scm_legacy implementation with
scm_smc implementation.
Elliot Berman [Tue, 7 Jan 2020 21:04:21 +0000 (13:04 -0800)]
firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_call
Move SMCCC register filling to qcom_scm_call so that __scm_legacy_do
only needs to concern itself with retry mechanism. qcom_scm_call then is
responsible for translating qcom_scm_desc into the complete set of
register arguments and passing onto qcom_scm_call_do.
Elliot Berman [Tue, 7 Jan 2020 21:04:20 +0000 (13:04 -0800)]
firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls
Use qcom_scm_desc in non-atomic calls to remove legacy convention
details from every SCM wrapper function. Implementations were copied
from qcom_scm-64 and are functionally equivalent when using the
qcom_scm_desc and qcom_scm_res structs.
Improve the calling convention detection to use
__qcom_scm_is_call_available() and not blindly assume 32-bit mode if
the checks fails. BUG() if neither 32-bit or 64-bit mode works.
Elliot Berman [Tue, 7 Jan 2020 21:04:16 +0000 (13:04 -0800)]
firmware: qcom_scm-64: Move SMC register filling to qcom_scm_call_smccc
qcom_scm_call_smccc should be responsible for converting qcom_scm_desc
into arguments for smc call. Consolidate the dispersed logic to convert
qcom_scm_desc into smc arguments inside qcom_scm_call_smccc.
Elliot Berman [Tue, 7 Jan 2020 21:04:15 +0000 (13:04 -0800)]
firmware: qcom_scm-64: Add SCM results struct
Remove knowledge of arm_smccc_res struct from client wrappers so that
client wrappers only work QCOM SCM data structures. SCM calls may have
up to 3 arguments, so qcom_scm_call_smccc is responsible now for filling
those 3 arguments accordingly. This is necessary to support merging
legacy and SMC conventions in an upcoming patch.
Elliot Berman [Tue, 7 Jan 2020 21:04:14 +0000 (13:04 -0800)]
firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_desc
Service, command, and owner IDs are all part of qcom_scm_desc struct and
have no special reason to be a function argument (or hard-coded in the
case of owner [1]). Moving them to be part of qcom_scm_desc struct improves
readability.
[1]: Example of SCM function using owner vale other than hard-coded SIP value:
https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/soc/qcom/smcinvoke.c?h=kernel.lnx.4.9.r28-rel#n35
Elliot Berman [Tue, 7 Jan 2020 21:04:13 +0000 (13:04 -0800)]
firmware: qcom_scm-64: Make SMC macros less magical
Improve understandability of SMC macros by reversing the logic as they
are all functions of how many arguments can be shoved in registers and
how many SCM arguments are supported.
There aren't 4 register arguments because are 7 arguments that go into a
buffer - there are up to 7 arguments that are overflowed into a buffer
because only 4 registers are allocated for arguments.
Reviewed-by: Stephen Boyd <swboyd@chromium.org> Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-5-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Elliot Berman [Tue, 7 Jan 2020 21:04:11 +0000 (13:04 -0800)]
firmware: qcom_scm: Apply consistent naming scheme to command IDs
Create a consistent naming scheme for command IDs. The scheme is
QCOM_SCM_##svc_##cmd. Remove unused macros QCOM_SCM_FLAG_HLOS,
QCOM_SCM_FLAG_COLDBOOT_MC, QCOM_SCM_FLAG_WARMBOOT_MC,
QCOM_SCM_CMD_CORE_HOTPLUGGED, and QCOM_SCM_BOOT_ADDR_MC.
Elliot Berman [Tue, 7 Jan 2020 21:04:10 +0000 (13:04 -0800)]
firmware: qcom_scm: Rename macros and structures
Rename legacy-specific structures and macros with legacy prefix; rename
smc-specific structures and macros with smc prefix. This should make it
clearer which structures are generic to "SCM" and which are specfically
for implementing the convention.
soc: samsung: Rename Samsung and Exynos to lowercase
Fix up inconsistent usage of upper and lowercase letters in "Samsung"
and "Exynos" names.
"SAMSUNG" and "EXYNOS" are not abbreviations but regular trademarked
names. Therefore they should be written with lowercase letters starting
with capital letter.
The lowercase "Exynos" name is promoted by its manufacturer Samsung
Electronics Co., Ltd., in advertisement materials and on website.
Although advertisement materials usually use uppercase "SAMSUNG", the
lowercase version is used in all legal aspects (e.g. on Wikipedia and in
privacy/legal statements on
https://www.samsung.com/semiconductor/privacy-global/).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Olof Johansson [Mon, 6 Jan 2020 17:23:04 +0000 (09:23 -0800)]
Merge tag 'scmi-updates-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers
ARM SCMI updates for v5.6
1. Addition of multiple device support per protocol to enable use of
some procotols by multiple kernel subsystems simultaneously and
corresponding updates to the existing scmi drivers
2. Addition of trace events around the scmi transfer code to measure
any delays and capture anomalies that can also be used during
investigation of some platform firmware related issues
* tag 'scmi-updates-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
drivers: firmware: scmi: Extend SCMI transport layer by trace events
include: trace: Add SCMI header with trace events
reset: reset-scmi: Match scmi device by both name and protocol id
hwmon: (scmi-hwmon) Match scmi device by both name and protocol id
cpufreq: scmi: Match scmi device by both name and protocol id
clk: scmi: Match scmi device by both name and protocol id
firmware: arm_scmi: Skip protocol initialisation for additional devices
firmware: arm_scmi: Stash version in protocol init functions
firmware: arm_scmi: Match scmi device by both name and protocol id
firmware: arm_scmi: Add versions and identifier attributes using dev_groups
firmware: arm_scmi: Add names to scmi devices created
firmware: arm_scmi: Skip scmi mbox channel setup for addtional devices
firmware: arm_scmi: Add support for multiple device per protocol
soc: renesas: Add ARCH_R8A7795[01] for existing R-Car H3
Despite using the same compatible values ("r8a7795"-based) because of
historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+
(R8A77951) are really different SoCs, with different part numbers.
Reflect this in the SoC configuration, by adding CONFIG_ARCH_R8A77950
and CONFIG_ARCH_R8A77951 as new config symbols. These are intended to
replace CONFIG_ARCH_R8A7795, and will allow making support for early SoC
revisions optional.
Note that for now, CONFIG_ARCH_R8A7795 is retained, and just selects
CONFIG_ARCH_R8A77950 and CONFIG_ARCH_R8A77951. This relaxes
dependencies of other subsystems on the SoC configuration symbol, and
provides a smooth transition path for config files through "make
oldconfig".
Jim Quinlan [Fri, 3 Jan 2020 19:04:29 +0000 (11:04 -0800)]
reset: Add Broadcom STB RESCAL reset controller
On BCM7216 there is a special purpose reset controller named RESCAL
(reset calibration) which is necessary for SATA and PCIe0/1 to operate
correctly. This commit adds support for such a reset controller to be
available.
Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
BCM7216 has a special purpose RESCAL reset controller for its SATA and
PCIe0/1 instances. This is a simple reset controller with #reset-cells
set to 0.
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
[florian: Convert to YAML binding] Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
firmware: scm: Add stubs for OCMEM and restore_sec_cfg_available
Add few more stubs (for OCMEM-related functions and
qcom_scm_restore_sec_cfg_available()) in case of !CONFIG_QCOM_SCM.
These are actually not necessary for builds but provide them for
completeness.
soc: bcm: brcmstb: biuctrl: Update programming for 7211
Add a matching entry for 7211 which can be programmed with the same
BIUCTRL settings as other Brahma-B53 based SoCs. While at it, rename the
function to include a72 in the name to reflect this applies to both
types of 64-bit capable CPUs that we support (Brahma-B53 and
Cortex-A72).
soc: bcm: brcmstb: biuctrl: Update layout for A72 on 7211
The BIUCTRL layout is a little different on 7211 which is equipped with
a Cortex-A72, account for those register offset differences. We will
match 7211 specifically in a subsequent commit.
Florian Fainelli [Tue, 10 Dec 2019 23:05:26 +0000 (15:05 -0800)]
soc: bcm: brcmstb: biuctrl: Tune interface for 7255 and 7216
7255 and 7216 are some of the latest chips that were produced and
support the full register range configuration for the BIU, add the two
entries to get the expected programming.
7260A0 and B0 are both supported, and 7260A0 has a small difference in
that it does not support the write-back control register, which is why
we have a different array of registers. Update the comment above
b53_cpubiuctrl_no_wb_regs to denote that difference.
Dilip Kota [Fri, 3 Jan 2020 10:00:18 +0000 (18:00 +0800)]
reset: intel: Add system reset controller driver
Add driver for the reset controller present on Intel
Gateway SoCs for performing reset management of the
devices present on the SoC. Driver also registers a
reset handler to peform the entire device reset.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Dilip Kota [Fri, 3 Jan 2020 10:00:17 +0000 (18:00 +0800)]
dt-bindings: reset: Add YAML schemas for the Intel Reset controller
Add YAML schemas for the reset controller on Intel
Gateway SoC.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Ard Biesheuvel [Mon, 9 Dec 2019 14:59:28 +0000 (15:59 +0100)]
optee: model OP-TEE as a platform device/driver
To simplify adding ACPI support to the OP-TEE driver, model it as
a platform driver. This will permit us to use the generic device
property layer for parsing additional properties, regardless of
whether DT or ACPI is being used.
Note that this change will result in the OP-TEE driver to be loaded
automatically on systems that advertise the presence of OP-TEE via
the device tree.
Ulf Hansson [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916
To enable the OS to better support PSCI OS initiated CPU suspend mode,
let's convert from the flattened layout to the hierarchical layout.
In the hierarchical layout, let's create a power domain provider per CPU
and describe the idle states for each CPU inside the power domain provider
node. To group the CPUs into a cluster, let's add another power domain
provider and make it act as the master domain. Note that, the CPU's idle
states remains compatible with "arm,idle-state", while the cluster's idle
state becomes compatible with "domain-idle-state".
Ulf Hansson [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
cpuidle: psci: Add support for PM domains by using genpd
When the hierarchical CPU topology layout is used in DT and the PSCI OSI
mode is supported by the PSCI FW, let's initialize a corresponding PM
domain topology by using genpd. This enables a CPU and a group of CPUs,
when attached to the topology, to be power-managed accordingly.
To trigger the attempt to initialize the genpd data structures let's use a
subsys_initcall, which should be early enough to allow CPUs, but also other
devices to be attached.
The initialization consists of parsing the PSCI OF node for the topology
and the "domain idle states" DT bindings. In case the idle states are
compatible with "domain-idle-state", the initialized genpd becomes
responsible of selecting an idle state for the PM domain, via assigning it
a genpd governor.
Note that, a successful initialization of the genpd data structures, is
followed by a call to psci_set_osi_mode(), as to try to enable the OSI mode
in the PSCI FW. In case this fails, we fall back into a degraded mode
rather than bailing out and returning error codes.
Ulf Hansson [Mon, 30 Dec 2019 12:59:30 +0000 (13:59 +0100)]
PM / Domains: Introduce a genpd OF helper that removes a subdomain
We already have the of_genpd_add_subdomain() helper, but no corresponding
of_genpd_remove_subdomain(), so let's add it. Subsequent changes starts to
make use of it.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Ulf Hansson [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
cpuidle: psci: Support CPU hotplug for the hierarchical model
When the hierarchical CPU topology is used and when a CPU is put offline,
that CPU prevents its PM domain from being powered off, which is because
genpd observes the corresponding attached device as being active from a
runtime PM point of view. Furthermore, any potential master PM domains are
also prevented from being powered off.
To address this limitation, let's add add a new CPU hotplug state
(CPUHP_AP_CPU_PM_STARTING) and register up/down callbacks for it, which
allows us to deal with runtime PM accordingly.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Ulf Hansson [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
cpuidle: psci: Manage runtime PM in the idle path
In case we have succeeded to attach a CPU to its PM domain, let's deploy
runtime PM support for the corresponding attached device, to allow the CPU
to be powered-managed accordingly.
The triggering point for when runtime PM reference counting should be done,
has been selected to the deepest idle state for the CPU. However, from the
hierarchical point view, there may be good reasons to do runtime PM
reference counting even on shallower idle states, but at this point this
isn't supported, mainly due to limitations set by the generic PM domain.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Ulf Hansson [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
cpuidle: psci: Prepare to use OS initiated suspend mode via PM domains
The per CPU variable psci_power_state, contains an array of fixed values,
which reflects the corresponding arm,psci-suspend-param parsed from DT, for
each of the available CPU idle states.
This isn't sufficient when using the hierarchical CPU topology in DT, in
combination with having PSCI OS initiated (OSI) mode enabled. More
precisely, in OSI mode, Linux is responsible of telling the PSCI FW what
idle state the cluster (a group of CPUs) should enter, while in PSCI
Platform Coordinated (PC) mode, each CPU independently votes for an idle
state of the cluster.
For this reason, introduce a per CPU variable called domain_state and
implement two helper functions to read/write its value. Then let the
domain_state take precedence over the regular selected state, when entering
and idle state.
To avoid executing the above OSI specific code in the ->enter() callback,
while operating in the default PSCI Platform Coordinated mode, let's also
add a new enter-function and use it for OSI.
Ulf Hansson [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
cpuidle: psci: Attach CPU devices to their PM domains
In order to enable a CPU to be power managed through its PM domain, let's
try to attach it by calling psci_dt_attach_cpu() during the cpuidle
initialization.
psci_dt_attach_cpu() returns a pointer to the attached struct device, which
later should be used for runtime PM, hence we need to store it somewhere.
Rather than adding yet another per CPU variable, let's create a per CPU
struct to collect the relevant per CPU variables.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Ulf Hansson [Mon, 28 Oct 2019 15:32:23 +0000 (16:32 +0100)]
cpuidle: psci: Add a helper to attach a CPU to its PM domain
Introduce a PSCI DT helper function, psci_dt_attach_cpu(), which takes a
CPU number as an in-parameter and tries to attach the CPU's struct device
to its corresponding PM domain.
Let's makes use of dev_pm_domain_attach_by_name(), as it allows us to
specify "psci" as the "name" of the PM domain to attach to. Additionally,
let's also prepare the attached device to be power managed via runtime PM.
Note that, the implementation of the new helper function is in a new
separate c-file, which may seems a bit too much at this point. However,
subsequent changes that implements the remaining part of the PM domain
support for cpuidle-psci, helps to justify this split.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Ulf Hansson [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
cpuidle: psci: Support hierarchical CPU idle states
Currently CPU's idle states are represented using the flattened model.
Let's add support for the hierarchical layout, via converting to use
of_get_cpu_state_node().
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Ulf Hansson [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
cpuidle: psci: Simplify OF parsing of CPU idle state nodes
Iterating through the idle state nodes in DT, to find out the number of
states that needs to be allocated is unnecessary, as it has already been
done from dt_init_idle_driver(). Therefore, drop the iteration and use the
number we already have at hand.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Lina Iyer [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
cpuidle: dt: Support hierarchical CPU idle states
Currently CPU's idle states are represented using the flattened model.
Let's add support for the hierarchical layout, via converting to use
of_get_cpu_state_node().
Suggested-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Co-developed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Ulf Hansson [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
of: base: Add of_get_cpu_state_node() to get idle states for a CPU node
The CPU's idle state nodes are currently parsed at the common cpuidle DT
library, but also when initializing data for specific CPU idle operations,
as in the PSCI cpuidle driver case and qcom-spm cpuidle case.
To avoid open-coding, let's introduce of_get_cpu_state_node(), which takes
the device node for the CPU and the index to the requested idle state node,
as in-parameters. In case a corresponding idle state node is found, it
returns the node with the refcount incremented for it, else it returns
NULL.
Moreover, for PSCI there are two options to describe the CPU's idle states
[1], either via a flattened description or a hierarchical layout. Hence,
let's take both options into account.
Ulf Hansson [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
firmware: psci: Export functions to manage the OSI mode
To allow subsequent changes to implement support for OSI mode through the
cpuidle-psci driver, export the existing psci_has_osi_support(). Export
also a new function, psci_set_osi_mode(), that allows its caller to enable
the OS-initiated CPU-suspend mode in the PSCI FW.
To deal with backwards compatibility for a kernel started through a kexec
call, default to set the CPU-suspend mode to the Platform Coordinated mode
during boot.
Ulf Hansson [Thu, 10 Oct 2019 10:01:48 +0000 (12:01 +0200)]
dt: psci: Update DT bindings to support hierarchical PSCI states
Update PSCI DT bindings to allow to represent idle states for CPUs and the
CPU topology, by using a hierarchical layout. Primarily this is done by
re-using the existing DT bindings for PM domains [1] and for PM domain idle
states [2].
Let's also add an example into the document for the PSCI DT bindings, to
clearly show the new hierarchical based layout. The currently supported
flattened layout, is already described in the ARM idle states bindings [3],
so let's leave that as is.
Sudeep Holla [Thu, 24 Oct 2019 15:18:34 +0000 (16:18 +0100)]
cpuidle: psci: Align psci_power_state count with idle state count
Instead of allocating 'n-1' states in psci_power_state to manage 'n'
idle states which include "ARM WFI" state, it would be simpler to have
1:1 mapping between psci_power_state and cpuidle driver states.
ARM WFI state(i.e. idx == 0) is handled specially in the generic macro
CPU_PM_CPU_IDLE_ENTER_PARAM and hence state[-1] is not possible. However
for sake of code readability, it is better to have 1:1 mapping and not
use [idx - 1] to access psci_power_state corresponding to driver cpuidle
state for idx.
psci_power_state[0] is default initialised to 0 and is never accessed
while entering WFI state.
Reported-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Kunihiko Hayashi [Fri, 29 Nov 2019 04:19:19 +0000 (13:19 +0900)]
reset: uniphier: Add SCSSI reset control for each channel
SCSSI has reset controls for each channel in the SoCs newer than Pro4,
so this adds missing reset controls for channel 1, 2 and 3. And more, this
moves MCSSI reset ID after SCSSI.
Fixes: 6b39fd590aeb ("reset: uniphier: add reset control support for SPI") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
__devm_reset_control_get() and devm_reset_control_array_get() are very
similar, but they do not look similar, due to inverted logic.
Make them more similar, following the "bail out early" paradigm.
Adjust the logic and flow in devm_reset_controller_register() to match
the two other functions.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Lukasz Luba [Tue, 17 Dec 2019 13:43:45 +0000 (13:43 +0000)]
drivers: firmware: scmi: Extend SCMI transport layer by trace events
The SCMI transport layer communicates via mailboxes and shared memory with
firmware running on a microcontroller. It is platform specific how long it
takes to pass a SCMI message. The most sensitive requests are coming from
CPUFreq subsystem, which might be used by the scheduler.
Thus, there is a need to measure these delays and capture anomalies.
This change introduces trace events wrapped around transfer code.
According to Jim's suggestion a unique transfer_id is to distinguish
similar entries which might have the same message id, protocol id and
sequence. This is a case then there are some timeouts in transfers.
Suggested-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Lukasz Luba <lukasz.luba@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
projects / linux.git / log