Arnd Bergmann [Fri, 1 Mar 2019 14:00:40 +0000 (15:00 +0100)]
Merge tag 'tee-misc-for-v5.1' of https://git.linaro.org/people/jens.wiklander/linux-tee into arm/drivers
OP-TEE driver
- dual license for optee_msg.h and optee_smc.h
Generic
- add cancellation support to client interface
* tag 'tee-misc-for-v5.1' of https://git.linaro.org/people/jens.wiklander/linux-tee:
tee: optee: update optee_msg.h and optee_smc.h to dual license
tee: add cancellation support to client interface
tee: optee: update optee_msg.h and optee_smc.h to dual license
The files optee_msg.h and optee_smc.h (under drivers/tee/optee) contain
information originating from the OP-TEE OS project [1] [2], where the
licensing terms are BSD 2-Clause. Therefore, apply a dual license to
those files.
Igor Opaniuk [Thu, 24 Jan 2019 17:32:31 +0000 (19:32 +0200)]
tee: add cancellation support to client interface
Add support of cancellation request to the TEE kernel internal
client interface. Can be used by software TPM drivers, that leverage
TEE under the hood (for instance TPM2.0 mobile profile), for requesting
cancellation of time-consuming operations (RSA key-pair generation etc.).
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
YueHaibing [Tue, 19 Feb 2019 07:04:28 +0000 (15:04 +0800)]
tee: optee: Fix unsigned comparison with less than zero
The return from the call to tee_client_invoke_func can be a
negative error code however this is being assigned to an
unsigned variable 'ret' hence the check is always false.
Fix this by making 'ret' an int.
Detected by Coccinelle ("Unsigned expression compared with zero:
ret < 0")
YueHaibing [Tue, 19 Feb 2019 06:33:02 +0000 (14:33 +0800)]
hwrng: Fix unsigned comparison with less than zero
The return from the call to tee_client_invoke_func can be a
negative error code however this is being assigned to an
unsigned variable 'ret' hence the check is always false.
Fix this by making 'ret' an int.
Detected by Coccinelle ("Unsigned expression compared with zero:
ret < 0")
hwrng: optee: Initialize some structs using memset instead of braces
Clang warns:
drivers/char/hw_random/optee-rng.c:80:31: warning: suggest braces around
initialization of subobject [-Wmissing-braces]
struct tee_param param[4] = {0};
^
{}
drivers/char/hw_random/optee-rng.c:177:31: warning: suggest braces
around initialization of subobject [-Wmissing-braces]
struct tee_param param[4] = {0};
^
{}
drivers/char/hw_random/optee-rng.c:212:48: warning: suggest braces
around initialization of subobject [-Wmissing-braces]
struct tee_ioctl_open_session_arg sess_arg = {0};
^
{}
3 warnings generated.
One way to fix these warnings is to add additional braces like Clang
suggests; however, there has been a bit of push back from some
maintainers, who just prefer memset as it is unambiguous, doesn't
depend on a particular compiler version, and properly initializes all
subobjects [1][2]. Do that here so there are no more warnings.
tee: optee: Initialize some structs using memset instead of braces
Clang warns:
drivers/tee/optee/device.c:39:31: warning: suggest braces around
initialization of subobject [-Wmissing-braces]
struct tee_param param[4] = {0};
^
{}
drivers/tee/optee/device.c:92:48: warning: suggest braces around
initialization of subobject [-Wmissing-braces]
struct tee_ioctl_open_session_arg sess_arg = {0};
^
{}
2 warnings generated.
One way to fix these warnings is to add additional braces like Clang
suggests; however, there has been a bit of push back from some
maintainers, who just prefer memset as it is unambiguous, doesn't
depend on a particular compiler version, and properly initializes all
subobjects [1][2]. Do that here so there are no more warnings.
Arnd Bergmann [Wed, 20 Feb 2019 15:12:49 +0000 (16:12 +0100)]
Merge tag 'soc-fsl-next-v5.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers
NXP/FSL SoC driver updates for v5.1 take3
DPIO driver
- fixed a use after free problem
- fixed a memory leak on error path
* tag 'soc-fsl-next-v5.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: dpio: fix memory leak of a struct qbman on error exit path
soc: fsl: dpio: Use after free in dpaa2_dpio_remove()
Arnd Bergmann [Fri, 15 Feb 2019 19:49:56 +0000 (20:49 +0100)]
Merge tag 'qcom-drivers-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/drivers
Qualcomm ARM Based Driver Updates for v5.1 - Part 2
* Fixups/Cleanup for Qualcomm LLCC
* tag 'qcom-drivers-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
qcom: soc: llcc-slice: Consolidate some code
qcom: soc: llcc-slice: Clear the global drv_data pointer on error
Arnd Bergmann [Fri, 15 Feb 2019 17:01:47 +0000 (18:01 +0100)]
Merge tag 'drivers_soc_for_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/drivers
soc: ti: couple of non critical fixes for v5.1
- Fix the Clang warning for enum in Navigator dma
- Simplify code in ti_sci with DEFINE_SHOW_ATTRIBUTE macro
* tag 'drivers_soc_for_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
soc: ti: knav_dma: Use proper enum in pktdma_init_chan
firmware: ti_sci: Change to use DEFINE_SHOW_ATTRIBUTE macro
Arnd Bergmann [Fri, 15 Feb 2019 17:00:42 +0000 (18:00 +0100)]
Merge tag 'arm-soc/for-5.1/drivers' of https://github.com/Broadcom/stblinux into arm/drivers
This pull request contains Broadcom ARM/ARM64/MIPS based SoCs changes
for 5.1, please pull the following:
- Stefan updates the BCM2835 SoC driver with downstream properties and
uses that to implement a reboot notifier to tell the VC4 firmware when
Linux on the ARM CPU is rebooting
- Eric adds a proper power domain driver for the BCM283x SoCs and
updates a bunch of drivers to have a better and clearer Device Tree
definition to support power domains/breaking up of functionality. This
requires converting the existing watchdog driver into a MFD and then
breaking up the functionality into separate drivers and finally
updating the DTS files to leverage the power domains information.
- Wei provides a fix for making a symbol static
* tag 'arm-soc/for-5.1/drivers' of https://github.com/Broadcom/stblinux:
ARM: bcm283x: Switch V3D over to using the PM driver instead of firmware.
ARM: bcm283x: Extend the WDT DT node out to cover the whole PM block. (v4)
soc: bcm: bcm2835-pm: Make local symbol static
soc: bcm: Make PM driver default for BCM2835
soc: bcm: bcm2835-pm: Add support for power domains under a new binding.
bcm2835-pm: Move bcm2835-watchdog's DT probe to an MFD.
dt-bindings: soc: Add a new binding for the BCM2835 PM node. (v4)
firmware: raspberrypi: notify VC4 firmware of a reboot
soc: bcm2835: sync firmware properties with downstream
Arnd Bergmann [Fri, 15 Feb 2019 16:58:41 +0000 (17:58 +0100)]
Merge tag 'qcom-drivers-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/drivers
Qualcomm ARM Based Driver Updates for v5.1
* Add Qualcomm RPMh power domain driver and related changes
* Fix issues with sleep/wake sets and batch API in RPMh
* Update MAINTAINERS Qualcomm entry
* Fixup RMTFS-mem sysfs and uevents
* Fix error handling in GSBI
* Add SMD-RPM compatible entry for SDM660
* tag 'qcom-drivers-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
soc: qcom: smd-rpm: Add sdm660 compatible
soc: qcom: gsbi: Fix error handling in gsbi_probe()
soc: qcom: rpmh: Avoid accessing freed memory from batch API
drivers: qcom: rpmh: avoid sending sleep/wake sets immediately
soc: qcom: rmtfs-mem: Make sysfs attributes world-readable
soc: qcom: rmtfs-mem: Add class to enable uevents
soc: qcom: update config dependencies for QCOM_RPMPD
soc: qcom: rpmpd: Drop family A RPM dependency
MAINTAINERS: update list of qcom drivers
soc: qcom: rpmhpd: Mark mx as a parent for cx
soc: qcom: rpmhpd: Add RPMh power domain driver
soc: qcom: rpmpd: Add support for get/set performance state
soc: qcom: rpmpd: Add a Power domain driver to model corners
dt-bindings: power: Add qcom rpm power domain driver bindings
OPP: Add support for parsing the 'opp-level' property
dt-bindings: opp: Introduce opp-level bindings
Arnd Bergmann [Fri, 15 Feb 2019 16:57:49 +0000 (17:57 +0100)]
Merge tag 'tee-bus-for-5.1' of https://git.linaro.org/people/jens.wiklander/linux-tee into arm/drivers
Introduce TEE bus driver framework
- supp_nowait flag for non-blocking tee requests
- The tee bus driver framework
- OP-TEE TEE bus device enumeration support
- An OP-TEE based rng driver
* tag 'tee-bus-for-5.1' of https://git.linaro.org/people/jens.wiklander/linux-tee:
hwrng: add OP-TEE based rng driver
tee: optee: add TEE bus device enumeration support
tee: add bus driver framework for TEE based devices
tee: add supp_nowait flag in tee_context struct
Arnd Bergmann [Fri, 15 Feb 2019 16:30:13 +0000 (17:30 +0100)]
Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
clk: tegra: Changes for v5.1-rc1
This contains a couple of prerequisite patches to enable CPU frequency
scaling on Tegra210.
* tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210
clk: tegra: dfll: add CVB tables for Tegra210
clk: tegra: dfll: round down voltages based on alignment
clk: tegra: dfll: support PWM regulator control
clk: tegra: dfll: CVB calculation alignment with the regulator
clk: tegra: dfll: registration for multiple SoCs
Arnd Bergmann [Fri, 15 Feb 2019 16:26:16 +0000 (17:26 +0100)]
Merge tag 'tegra-for-5.1-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
cpufreq: tegra: Add support for Tegra210
This uses the DFLL clock support to enable CPU frequency scaling on
Tegra210.
* tag 'tegra-for-5.1-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
cpufreq: dt-platdev: add Tegra210 to blacklist
cpufreq: tegra124: extend to support Tegra210
cpufreq: tegra124: do not handle the CPU rail
Arnd Bergmann [Fri, 15 Feb 2019 16:24:05 +0000 (17:24 +0100)]
Merge tag 'tegra-for-5.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
soc/tegra: Changes for v5.1-rc1
This contains a couple of miscellaneous fixes for minor issues and a
largish rework of the PMC driver to make it work on systems where the
PMC has been locked down and can only be accessed from secure firmware.
* tag 'tegra-for-5.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: pmc: Support systems where PMC is marked secure
soc/tegra: pmc: Explicitly initialize all fields
soc/tegra: pmc: Make alignment consistent
soc/tegra: pmc: Pass struct tegra_pmc * where possible
soc/tegra: pmc: Make tegra_powergate_is_powered() a local function
soc/tegra: pmc: Add missing kerneldoc
soc/tegra: pmc: Sort includes alphabetically
soc/tegra: pmc: Use TEGRA186_ prefix for GPIO names
soc/tegra: fuse: Fix typo in tegra210_init_speedo_data
soc/tegra: fuse: Fix illegal free of IO base address
Arnd Bergmann [Fri, 15 Feb 2019 16:21:04 +0000 (17:21 +0100)]
Merge tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux into arm/drivers
Reset controller changes for v5.1
This adds the include/linux/reset directory to MAINTAINERS for reset
specific headers and adds headers for sunxi and socfpga in there to
get rid of a few extern function declarations.
There is a new reset driver for the Broadcom STB reset controller and
the i.MX7 system reset controller driver is extended to support i.MX8MQ
as well. Finally, there is a new header with reset id constants for
the Meson G12A SoC, which has a reset controller identical to Meson AXG
and thus can reuse its driver and DT bindings.
* tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux:
dt-bindings: reset: meson: add g12a bindings
reset: imx7: Add support for i.MX8MQ IP block variant
reset: imx7: Add plubming to support multiple IP variants
reset: Add Broadcom STB SW_INIT reset controller driver
dt-bindings: reset: Add document for Broadcom STB reset controller
reset: socfpga: declare socfpga_reset_init in a header file
reset: sunxi: declare sun6i_reset_init in a header file
MAINTAINERS: use include/linux/reset for reset controller related headers
dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs
Arnd Bergmann [Fri, 15 Feb 2019 16:19:19 +0000 (17:19 +0100)]
Merge tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/drivers
Amlogic: driver updates for v5.1
- clock measure: add support for G12a SoC family
- misc. fixes
* tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
soc: amlogic: clk-measure: add axg and g12a support
dt-bindings: amlogic: add new compatible devices to clk_measure
soc: amlogic: canvas: Fix meson_canvas_get when probe failed
soc: amlogic: add missing of_node_put()
Arnd Bergmann [Fri, 15 Feb 2019 16:17:33 +0000 (17:17 +0100)]
Merge tag 'imx-drivers-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.1:
- Do not get GPCv2 driver depend on SOC_IMX8MQ since the driver is
going to be used on more SoCs than just i.MX8MQ.
- Add power domain information into SCU bindings document.
- Add support of start/stop a CPU into imx firmware driver.
- Support multiple address ranges per child node for imx-weim bus
driver.
* tag 'imx-drivers-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
firmware: imx: Add support to start/stop a CPU
soc: imx: Break dependency on SOC_IMX8MQ for GPCv2
firmware: imx: scu-pd: add fallback compatible string support
dt-bindings: fsl: scu: add imx8qm scu power domain support
dt-bindings: fsl: scu: add fallback compatible string for power domain
bus: imx-weim: guard against timing configuration conflicts
bus: imx-weim: support multiple address ranges per child node
dt-bindings: bus: imx-weim: document multiple address ranges per child node
soc: imx: gpcv2: handle reset clocks
soc: imx: gpcv2: handle additional power-down bits in handshake register
Jordan Crouse [Tue, 11 Dec 2018 20:07:46 +0000 (13:07 -0700)]
qcom: soc: llcc-slice: Consolidate some code
Make the code a little bit clearer (and use less gotos)
by consolidating some of the initialization.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Jordan Crouse [Tue, 11 Dec 2018 20:07:45 +0000 (13:07 -0700)]
qcom: soc: llcc-slice: Clear the global drv_data pointer on error
Currently the data structure for llc-slice is devm allocated and
stored as a global but never cleared if the probe function fails.
This is a problem because devm managed memory gets freed on probe
failure the API functions could access the pointer after it has been
freed.
Initialize the drv_data pointer to an error and reset it to an error
on probe failure or device destroy and add protection to the API
functions to make sure the memory doesn't get accessed.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Jolly Shah [Fri, 1 Feb 2019 22:08:50 +0000 (14:08 -0800)]
drivers: soc: xilinx: Add ZynqMP power domain driver
The zynqmp-genpd driver communicates the usage requirements
for logical power domains / devices to the platform FW.
FW is responsible for choosing appropriate power states,
taking Linux' usage information into account.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Fri, 1 Feb 2019 22:08:49 +0000 (14:08 -0800)]
firmware: xilinx: Add APIs to control node status/power
Add Xilinx ZynqMP firmware APIs to control node status
and power. These APIs allows turning on/off power domain
and setting capabilities of devices present in power domain.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Fri, 1 Feb 2019 22:08:48 +0000 (14:08 -0800)]
dt-bindings: power: Add ZynqMP power domain bindings
Add documentation to describe ZynqMP power domain bindings.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Tue, 29 Jan 2019 20:38:21 +0000 (12:38 -0800)]
drivers: soc: xilinx: Add ZynqMP PM driver
Add ZynqMP PM driver. PM driver provides power management
support for ZynqMP.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jolly Shah [Tue, 29 Jan 2019 20:38:20 +0000 (12:38 -0800)]
firmware: xilinx: Implement ZynqMP power management APIs
Add Xilinx ZynqMP firmware APIs to set suspend mode
and inform firmware that master has initialized its
own power management.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Tue, 29 Jan 2019 20:38:19 +0000 (12:38 -0800)]
dt-bindings: soc: Add ZynqMP PM bindings
Add documentation to describe Xilinx ZynqMP power management
bindings.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
John Garry [Thu, 3 Jan 2019 11:57:02 +0000 (19:57 +0800)]
bus: hisi_lpc: Don't fail probe for unrecognised child devices
Currently for ACPI-based FW we fail the probe for an unrecognised child
HID.
However, there is FW in the field with LPC child devices having fake HIDs,
namely "IPI0002", which was an IPMI device invented to support the
initial out-of-tree LPC host driver, different from the final mainline
version.
To provide compatibility support for these dodgy FWs, just discard the
unrecognised HIDs instead of failing the probe altogether.
Tested-by: Zengruan Ye <yezengruan@huawei.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Jerome Brunet [Fri, 18 Jan 2019 10:34:21 +0000 (11:34 +0100)]
soc: amlogic: clk-measure: add axg and g12a support
Add support for the axg and g12a SoC family in amlogic clk measure
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[khilman: squashed some fixups from Martin] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Thierry Reding [Thu, 7 Feb 2019 11:50:06 +0000 (12:50 +0100)]
firmware/tegra: Enable Tegra186 BPMP support on Tegra194
The BPMP implementation on Tegra194 is mostly compatible with the
implementation on Tegra186, so make sure the latter is available when
support for Tegra194 is enabled.
Suggested-by: Timo Alho <talho@nvidia.com> Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Thu, 7 Feb 2019 11:50:05 +0000 (12:50 +0100)]
firmware: tegra: Conditionally support SoC generations
Only include support for Tegra210 and Tegra186 in the BPMP driver if
support for those SoCs was selected. This fixes a build failure seen
on 32-bit ARM allmodconfig builds, but could also happen on 64-bit
ARM builds if either Tegra210 or Tegra186 were not selected.
Reported-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Joseph Lo [Fri, 4 Jan 2019 03:06:55 +0000 (11:06 +0800)]
cpufreq: dt-platdev: add Tegra210 to blacklist
Tegra210 uses "tegra124-cpufreq" platform driver to register device data
for "cpufreq-dt" driver. So add it in the blacklist for
"cpufreq-dt-platdev" driver to drop that.
Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: linux-pm@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Joseph Lo [Fri, 4 Jan 2019 03:06:53 +0000 (11:06 +0800)]
cpufreq: tegra124: do not handle the CPU rail
The Tegra124 cpufreq driver has no information to handle the Vdd-CPU
rail. So this driver shouldn't handle for the CPU clock switching from
DFLL to other PLL clocks. It was designed to work on DFLL clock only,
which handle the frequency/voltage scaling in the background.
This patch removes the driver dependency of the CPU rail, as well as not
allow it to be built as a module and remove the removal function. So it
can keep working on DFLL clock.
Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: linux-pm@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210
Tegra210 has a DFLL as well and can share the majority of the code with
the Tegra124 implementation. So build the same code for both platforms.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Joseph Lo [Fri, 4 Jan 2019 03:06:51 +0000 (11:06 +0800)]
clk: tegra: dfll: add CVB tables for Tegra210
Add CVB tables with different chip characterization, so that we can
generate the customize OPP table that suitable for different chips with
different SKUs.
The parameter 'tune_high_min_millivolts' is first time introduced in
this patch, which didn't use in the DFLL driver for clock and voltage
tuning before. It will be used later when DFLL in high voltage range.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Joseph Lo [Fri, 4 Jan 2019 03:06:50 +0000 (11:06 +0800)]
clk: tegra: dfll: round down voltages based on alignment
When generating the OPP table, the voltages are round down with the
alignment from the regulator. The alignment should be applied for
voltages look up as well.
Based on the work of Penny Chiu <pchiu@nvidia.com>.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Joseph Lo [Fri, 4 Jan 2019 03:06:49 +0000 (11:06 +0800)]
clk: tegra: dfll: support PWM regulator control
The DFLL hardware supports two modes (I2C and PWM) for voltage control
when requesting a frequency. In this patch, we introduce PWM mode support.
To support that, we re-organize the LUT for unifying the table for both
cases of I2C and PWM mode. And generate that based on regulator info.
For the PWM-based regulator, we get this info from DT. And do the same as
the case of I2C LUT, which can help to map the PMIC voltage ID and voltages
that the regulator supported.
The other parts are the support code for initializing the DFLL hardware
to support PWM mode. Also, the register debugfs file is slightly
reworked to only show the i2c registers when I2C mode is in use.
Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>.
Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Joseph Lo [Fri, 4 Jan 2019 03:06:48 +0000 (11:06 +0800)]
clk: tegra: dfll: CVB calculation alignment with the regulator
The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset parameters depend
on the regulator supplying vdd-cpu, not on the specific Tegra SKU.
When using a PWM controlled regulator, the voltage step and offset are
determined by the regulator type in use. This is specified in DT. When
using an I2C controlled regulator, we can retrieve them from CPU regulator
Then pass this information to the CVB table calculation function.
Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>"
and "Alex Frid <afrid@nvidia.com>".
Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
In a future patch, support for the DFLL in Tegra210 will be introduced.
This requires support for more than 1 set of CVB and CPU max frequency
tables.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Dan Carpenter [Mon, 4 Feb 2019 14:10:05 +0000 (17:10 +0300)]
soc: fsl: dpio: Use after free in dpaa2_dpio_remove()
The dpaa2_io_down(priv->io) call frees "priv->io" so I've shifted the
code around a little bit to avoid the use after free.
Fixes: 991e873223e9 ("soc: fsl: dpio: use a cpumask to identify which cpus are unused") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
Stephen Boyd [Tue, 15 Jan 2019 22:54:47 +0000 (14:54 -0800)]
soc: qcom: rpmh: Avoid accessing freed memory from batch API
Using the batch API from the interconnect driver sometimes leads to a
KASAN error due to an access to freed memory. This is easier to trigger
with threadirqs on the kernel commandline.
BUG: KASAN: use-after-free in rpmh_tx_done+0x114/0x12c
Read of size 1 at addr fffffff51414ad84 by task irq/110-apps_rs/57
Memory state around the buggy address: fffffff51414ac80: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fffffff51414ad00: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
>fffffff51414ad80: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
^ fffffff51414ae00: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fffffff51414ae80: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
The batch API sets the same completion for each rpmh message that's sent
and then loops through all the messages and waits for that single
completion declared on the stack to be completed before returning from
the function and freeing the message structures. Unfortunately, some
messages may still be in process and 'stuck' in the TCS. At some later
point, the tcs_tx_done() interrupt will run and try to process messages
that have already been freed at the end of rpmh_write_batch(). This will
in turn access the 'needs_free' member of the rpmh_request structure and
cause KASAN to complain. Furthermore, if there's a message that's
completed in rpmh_tx_done() and freed immediately after the complete()
call is made we'll be racing with potentially freed memory when
accessing the 'needs_free' member:
Let's fix this by allocating a chunk of completions for each message and
waiting for all of them to be completed before returning from the batch
API. Alternatively, we could wait for the last message in the batch, but
that may be a more complicated change because it looks like
tcs_tx_done() just iterates through the indices of the queue and
completes each message instead of tracking the last inserted message and
completing that first.
Fixes: c8790cb6da58 ("drivers: qcom: rpmh: add support for batch RPMH request") Cc: Lina Iyer <ilina@codeaurora.org> Cc: "Raju P.L.S.S.S.N" <rplsssn@codeaurora.org> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Evan Green <evgreen@chromium.org> Cc: stable@vger.kernel.org Reviewed-by: Lina Iyer <ilina@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Fix the redundant call being made to send the sleep and wake requests
immediately to the controller.
As per the patch [1], the sleep and wake request votes are cached in
rpmh controller and sent during rpmh_flush(). These requests needs to be
sent only during entry of deeper system low power modes or suspend.
Evan Green [Thu, 3 Jan 2019 00:02:13 +0000 (16:02 -0800)]
soc: qcom: rmtfs-mem: Make sysfs attributes world-readable
In order to run an rmtfs daemon as an unprivileged user, that user would
need access to the phys_addr and size sysfs attributes. Sharing these
attributes with unprivileged users doesn't really leak anything
sensitive, since if you have access to physical memory, the jig is
up anyway.
Make those attributes readable by all.
Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Evan Green [Thu, 3 Jan 2019 00:02:12 +0000 (16:02 -0800)]
soc: qcom: rmtfs-mem: Add class to enable uevents
Currently the qcom_rmtfs_memN devices are entirely invisible to the udev world.
Add a class to the rmtfs device so that uevents fire when the device is added.
Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Sumit Garg [Tue, 29 Jan 2019 05:49:38 +0000 (11:19 +0530)]
hwrng: add OP-TEE based rng driver
On ARM SoC's with TrustZone enabled, peripherals like entropy sources
might not be accessible to normal world (linux in this case) and rather
accessible to secure world (OP-TEE in this case) only. So this driver
aims to provides a generic interface to OP-TEE based random number
generator service.
This driver registers on TEE bus to interact with OP-TEE based rng
device/service.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Sumit Garg [Tue, 29 Jan 2019 05:49:37 +0000 (11:19 +0530)]
tee: optee: add TEE bus device enumeration support
OP-TEE provides a pseudo TA to enumerate TAs which can act as devices/
services for TEE bus. So implement device enumeration using invoke
function: PTA_CMD_GET_DEVICES provided by pseudo TA to fetch array of
device UUIDs. Also register these enumerated devices with TEE bus as
"optee-clntX" device.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
[jw: fix optee_enumerate_devices() with no devices found] Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Sumit Garg [Tue, 29 Jan 2019 05:49:35 +0000 (11:19 +0530)]
tee: add bus driver framework for TEE based devices
Introduce a generic TEE bus driver concept for TEE based kernel drivers
which would like to communicate with TEE based devices/services. Also
add support in module device table for these new TEE based devices.
In this TEE bus concept, devices/services are identified via Universally
Unique Identifier (UUID) and drivers register a table of device UUIDs
which they can support.
So this TEE bus framework registers following apis:
- match(): Iterates over the driver UUID table to find a corresponding
match for device UUID. If a match is found, then this particular device
is probed via corresponding probe api registered by the driver. This
process happens whenever a device or a driver is registered with TEE
bus.
- uevent(): Notifies user-space (udev) whenever a new device is registered
on this bus for auto-loading of modularized drivers.
Also this framework allows for device enumeration to be specific to
corresponding TEE implementation like OP-TEE etc.
Sumit Garg [Tue, 29 Jan 2019 05:49:36 +0000 (11:19 +0530)]
tee: add supp_nowait flag in tee_context struct
This flag indicates that requests in this context should not wait for
tee-supplicant daemon to be started if not present and just return
with an error code. It is needed for requests which should be
non-blocking in nature like ones arising from TEE based kernel drivers
or any in kernel api that uses TEE internal client interface.
Eric Anholt [Wed, 12 Dec 2018 23:51:50 +0000 (15:51 -0800)]
ARM: bcm283x: Switch V3D over to using the PM driver instead of firmware.
The GRAFX domain only contains V3D, and this driver should be the only
accessor of V3D (firmware usage gets disabled when V3D is in the DT),
so we can safely make Linux control the GRAFX and GRAFX_V3D power
domains.
Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Eric Anholt [Wed, 12 Dec 2018 23:51:49 +0000 (15:51 -0800)]
ARM: bcm283x: Extend the WDT DT node out to cover the whole PM block. (v4)
It was covering part of the PM block's range, up to the WDT regs. To
support the rest of the PM block's functionality, we need the full
register range plus the AXI Async Bridge regs for PM sequencing.
This doesn't convert any of the consumers over to the new binding yet,
since we will need to be careful in coordinating our usage of firmware
services that might power domains on and off versus the bcm2835-pm
driver's access of those same domains.
Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Wei Yongjun [Wed, 16 Jan 2019 05:44:17 +0000 (05:44 +0000)]
soc: bcm: bcm2835-pm: Make local symbol static
Fixes the following sparse warning:
drivers/soc/bcm/bcm2835-power.c:556:32: warning:
symbol 'bcm2835_reset_ops' was not declared. Should it be static?
Fixes: 670c672608a1 ("soc: bcm: bcm2835-pm: Add support for power domains under a new binding.") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Arnd Bergmann [Wed, 30 Jan 2019 22:01:07 +0000 (23:01 +0100)]
Merge tag 'soc-fsl-next-v5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers
NXP/FSL SoC driver updates for v5.1
DPIO driver
- Clean up the remove path in the dpio driver so that successive
bind/unbind commands behave properly
- Add the ability to automatically create a device link between a
consumer device on the fsl-mc bus and a supplier one
- Add prefetch to dpio dequeue to improve performance
- Update the type of dpio APIs to align with buffer pool id register
field
guts driver
- Prevent allocation failure by reuse the machine type data from device
tree directly
* tag 'soc-fsl-next-v5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: guts: reuse machine name from device tree
soc: fsl: dpio: Change bpid type to u16
soc: fsl: dpio: Add prefetch instruction
bus: fsl-mc: automatically add a device_link on fsl_mc_[portal,object]_allocate
soc: fsl: dpio: add a device_link at dpaa2_io_service_register
soc: fsl: dpio: store a backpointer to the device backing the dpaa2_io
soc: fsl: dpio: keep a per dpio device MC portal
soc: fsl: dpio: perform DPIO Reset on Probe
soc: fsl: dpio: use a cpumask to identify which cpus are unused
soc: fsl: dpio: cleanup the cpu array on dpaa2_io_down
soc: ti: knav_dma: Use proper enum in pktdma_init_chan
Clang warns when one enumerated type is implicitly converted to another:
drivers/soc/ti/knav_dma.c:601:20: warning: implicit conversion from
enumeration type 'enum dma_data_direction' to different enumeration type
'enum dma_transfer_direction' [-Wenum-conversion]
chan->direction = DMA_NONE;
~ ^~~~~~~~
1 warning generated.
While DMA_NONE and DMA_TRANS_NONE have different values, there is no
functional change because direction is never checked against DMA_NONE,
only against DMA_MEM_TO_DEV and DMA_DEV_TO_MEM.
reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller.
Add a reset controller driver for Xilinx Zynq UltraScale+ MPSoC.
The zynqmp reset-controller has the ability to reset lines
connected to different blocks and peripheral in the Soc.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dt-bindings: reset: Add bindings for ZynqMP reset driver
Add documentation to describe Xilinx ZynqMP reset driver
bindings.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for resetting blocks through the Linux reset controller
subsystem when reset lines are provided through a SW_INIT-style reset
controller on Broadcom STB SoCs.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Philipp Zabel [Thu, 13 Dec 2018 11:24:36 +0000 (12:24 +0100)]
reset: socfpga: declare socfpga_reset_init in a header file
Avoid declaring extern functions in c files. To make sure function
definition and usage don't get out of sync, declare socfpga_reset_init
in a common header.
Suggested-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Philipp Zabel [Thu, 13 Dec 2018 11:22:32 +0000 (12:22 +0100)]
reset: sunxi: declare sun6i_reset_init in a header file
Avoid declaring extern functions in c files. To make sure function
definition and usage don't get out of sync, declare sun6i_reset_init
in a common header.
Suggested-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Philipp Zabel [Thu, 13 Dec 2018 11:26:54 +0000 (12:26 +0100)]
MAINTAINERS: use include/linux/reset for reset controller related headers
The include/linux/reset directory currently contains one header with
helper functions for Broadcom BCM63xx PMB, which can control reset
lines to on-chip peripherals. Even though that driver doesn't use the
reset controller framework, the the directory can be shared with other
reset controller drivers that do.
Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Linus Torvalds [Sun, 27 Jan 2019 20:02:00 +0000 (12:02 -0800)]
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Thomas Gleixner:
"A set of fixes for x86:
- Fix the swapped outb() parameters in the KASLR code
- Fix the PKEY handling at fork which missed to preserve the pkey
state for the child. Comes with a test case to validate that.
- Fix the entry stack handling for XEN PV to respect that XEN PV
systems enter the function already on the current thread stack and
not on the trampoline.
- Fix kexec load failure caused by using a stale value when the
kexec_buf structure is reused for subsequent allocations.
- Fix a bogus sizeof() in the memory encryption code
- Enforce PCI dependency for the Intel Low Power Subsystem
- Enforce PCI_LOCKLESS_CONFIG when PCI is enabled"
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/Kconfig: Select PCI_LOCKLESS_CONFIG if PCI is enabled
x86/entry/64/compat: Fix stack switching for XEN PV
x86/kexec: Fix a kexec_file_load() failure
x86/mm/mem_encrypt: Fix erroneous sizeof()
x86/selftests/pkeys: Fork() to check for state being preserved
x86/pkeys: Properly copy pkey state at fork()
x86/kaslr: Fix incorrect i8254 outb() parameters
x86/intel/lpss: Make PCI dependency explicit
Linus Torvalds [Sun, 27 Jan 2019 19:57:46 +0000 (11:57 -0800)]
Merge branch 'x86-timers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 timer fixes from Thomas Gleixner:
"Two commits which were missed to be sent during the merge window.
- The TSC calibration fix turns out to be more urgent as recent
Skylake-X systems seem to have massive trouble with calibration
disturbance. This should go back into stable for that reason and it
the risk of breakage is rather low.
- Drop an unused define"
* 'x86-timers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/hpet: Remove unused FSEC_PER_NSEC define
x86/tsc: Make calibration refinement more robust
Linus Torvalds [Sun, 27 Jan 2019 19:55:06 +0000 (11:55 -0800)]
Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer fix from Thomas Glexiner:
"A single regression fix to address the unintended breakage of posix
cpu timers.
This is caused by a new sanity check in the common code, which fails
for posix cpu timers under certain conditions because the posix cpu
timer code never updates the variable which is checked"
* 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
posix-cpu-timers: Unbreak timer rearming
Linus Torvalds [Sun, 27 Jan 2019 19:25:38 +0000 (11:25 -0800)]
Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner:
"A small set of fixes for the interrupt subsystem:
- Fix a double increment in the irq descriptor allocator which
resulted in a sanity check only being done for every second
affinity mask
- Add a missing device tree translation in the stm32-exti driver.
Without that the interrupt association is completely wrong.
- Initialize the mutex in the GIC-V3 MBI driver
- Fix the alignment for aliasing devices in the GIC-V3-ITS driver so
multi MSI allocations work correctly
- Ensure that the initial affinity of a interrupt is not empty at
startup time.
- Drop bogus include in the madera irq chip driver
- Fix KernelDoc regression"
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/gic-v3-its: Align PCI Multi-MSI allocation on their size
genirq/irqdesc: Fix double increment in alloc_descs()
genirq: Fix the kerneldoc comment for struct irq_affinity_desc
irqchip/madera: Drop GPIO includes
irqchip/gic-v3-mbi: Fix uninitialized mbi_lock
irqchip/stm32-exti: Add domain translate function
genirq: Make sure the initial affinity is not empty
Linus Torvalds [Sun, 27 Jan 2019 17:21:00 +0000 (09:21 -0800)]
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM fixes from Paolo Bonzini:
"Quite a few fixes for x86: nested virtualization save/restore, AMD
nested virtualization and virtual APIC, 32-bit fixes, an important fix
to restore operation on older processors, and a bunch of hyper-v
bugfixes. Several are marked stable.
There are also fixes for GCC warnings and for a GCC/objtool interaction"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: x86: Mark expected switch fall-throughs
KVM: x86: fix TRACE_INCLUDE_PATH and remove -I. header search paths
KVM: selftests: check returned evmcs version range
x86/kvm/hyper-v: nested_enable_evmcs() sets vmcs_version incorrectly
KVM: VMX: Move vmx_vcpu_run()'s VM-Enter asm blob to a helper function
kvm: selftests: Fix region overlap check in kvm_util
kvm: vmx: fix some -Wmissing-prototypes warnings
KVM: nSVM: clear events pending from svm_complete_interrupts() when exiting to L1
svm: Fix AVIC incomplete IPI emulation
svm: Add warning message for AVIC IPI invalid target
KVM: x86: WARN_ONCE if sending a PV IPI returns a fatal error
KVM: x86: Fix PV IPIs for 32-bit KVM host
x86/kvm/hyper-v: recommend using eVMCS only when it is enabled
x86/kvm/hyper-v: don't recommend doing reset via synthetic MSR
kvm: x86/vmx: Use kzalloc for cached_vmcs12
KVM: VMX: Use the correct field var when clearing VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
KVM: x86: Fix single-step debugging
x86/kvm/hyper-v: don't announce GUEST IDLE MSR support
Linus Torvalds [Sun, 27 Jan 2019 17:11:51 +0000 (09:11 -0800)]
Merge tag 'libnvdimm-fixes-5.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm
Pull libnvdimm fixes from Dan Williams:
"A fix for namespace label support for non-Intel NVDIMMs that implement
the ACPI standard label method.
This has apparently never worked and could wait for v5.1. However it
has enough visibility with hardware vendors [1] and distro bug
trackers [2], and low enough risk that I decided it should go in for
-rc4. The other fixups target the new, for v5.0, nvdimm security
functionality. The larger init path fixup closes a memory leak and a
potential userspace lockup due to missed notifications.
These have all soaked in -next for a week with no reported issues.
Summary:
- Fix support for NVDIMMs that implement the ACPI standard label
methods.
- Fix error handling for security overwrite (memory leak / userspace
hang condition), and another one-line security cleanup"
* tag 'libnvdimm-fixes-5.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm:
acpi/nfit: Fix command-supported detection
acpi/nfit: Block function zero DSMs
libnvdimm/security: Require nvdimm_security_setup_events() to succeed
nfit_test: fix security state pull for nvdimm security nfit_test
1) Count ttl-dropped frames properly in mac80211, from Bob Copeland.
2) Integer overflow in ktime handling of bcm can code, from Oliver
Hartkopp.
3) Fix RX desc handling wrt. hw checksumming in ravb, from Simon
Horman.
4) Various hash key fixes in hv_netvsc, from Haiyang Zhang.
5) Use after free in ax25, from Eric Dumazet.
6) Several fixes to the SSN support in SCTP, from Xin Long.
7) Do not process frames after a NAPI reschedule in ibmveth, from
Thomas Falcon.
8) Fix NLA_POLICY_NESTED arguments, from Johannes Berg.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (42 commits)
qed: Revert error handling changes.
cfg80211: extend range deviation for DMG
cfg80211: reg: remove warn_on for a normal case
mac80211: Add attribute aligned(2) to struct 'action'
mac80211: don't initiate TDLS connection if station is not associated to AP
nl80211: fix NLA_POLICY_NESTED() arguments
ibmveth: Do not process frames after calling napi_reschedule
net: dev_is_mac_header_xmit() true for ARPHRD_RAWIP
net: usb: asix: ax88772_bind return error when hw_reset fail
MAINTAINERS: Update cavium networking drivers
net/mlx4_core: Fix error handling when initializing CQ bufs in the driver
net/mlx4_core: Add masking for a few queries on HCA caps
sctp: set flow sport from saddr only when it's 0
sctp: set chunk transport correctly when it's a new asoc
sctp: improve the events for sctp stream adding
sctp: improve the events for sctp stream reset
ip_tunnel: Make none-tunnel-dst tunnel port work with lwtunnel
ax25: fix possible use-after-free
sfc: suppress duplicate nvmem partition types in efx_ef10_mtd_probe
hv_netvsc: fix typos in code comments
...
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