Olof Johansson [Mon, 11 Nov 2019 21:13:22 +0000 (13:13 -0800)]
Merge tag 'tegra-for-5.5-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
memory: tegra: Changes for v5.5-rc1
This contains a couple of fixes and adds support for EMC frequency
scaling on Tegra30.
* tag 'tegra-for-5.5-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
memory: tegra: Consolidate registers definition into common header
memory: tegra: Ensure timing control debug features are disabled
memory: tegra: Introduce Tegra30 EMC driver
memory: tegra: Do not handle error from wait_for_completion_timeout()
memory: tegra: Increase handshake timeout on Tegra20
memory: tegra: Print a brief info message about EMC timings
memory: tegra: Pre-configure debug register on Tegra20
memory: tegra: Include io.h instead of iopoll.h
memory: tegra: Adapt for Tegra20 clock driver changes
memory: tegra: Don't set EMC rate to maximum on probe for Tegra20
memory: tegra: Add gr2d and gr3d to DRM IOMMU group
memory: tegra: Set DMA mask based on supported address bits
clk: tegra: Add Tegra20/30 EMC clock implementation
Olof Johansson [Mon, 11 Nov 2019 21:09:34 +0000 (13:09 -0800)]
Merge tag 'hisi-drivers-for-5.5' of git://github.com/hisilicon/linux-hisi into arm/drivers
ARM64: hisi: SoC driver updates for 5.5
- check the LOGIC_PIO_INDIRECT region ops at registration instead of
in the IO port accessors to optimise the lib/ligic_pio.c
- add the hisi LPC driver to the build test for the other architectures
except ALPHA, C6X, HEXAGON and PARISC as they do not define {read,write}sb
by updating the hisi LPC Kconfig and adding a dummy PIO_INDIRECT_SIZE
- clean the sparse complains of the hisi LPC driver
- build logic_pio into a lib to avoid including in the vmlinux when not
referenced
* tag 'hisi-drivers-for-5.5' of git://github.com/hisilicon/linux-hisi:
logic_pio: Build into a library
bus: hisi_lpc: Expand build test coverage
bus: hisi_lpc: Clean some types
logic_pio: Define PIO_INDIRECT_SIZE for !CONFIG_INDIRECT_PIO
lib: logic_pio: Enforce LOGIC_PIO_INDIRECT region ops are set at registration
Olof Johansson [Mon, 11 Nov 2019 21:09:02 +0000 (13:09 -0800)]
Merge tag 'v5.4-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers
refactor code of mtk-scpsys
* tag 'v5.4-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
soc: mediatek: Refactor bus protection control
soc: mediatek: Refactor sram control
soc: mediatek: Refactor clock control
soc: mediatek: Refactor regulator control
soc: mediatek: Refactor polling timeout and documentation
Dmitry Osipenko [Sun, 11 Aug 2019 21:00:41 +0000 (00:00 +0300)]
memory: tegra: Ensure timing control debug features are disabled
Timing control debug features should be disabled at a boot time, but you
never now and hence it's better to disable them explicitly because some of
those features are crucial for the driver to do a proper thing.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Sun, 11 Aug 2019 21:00:40 +0000 (00:00 +0300)]
memory: tegra: Introduce Tegra30 EMC driver
Introduce driver for the External Memory Controller (EMC) found on Tegra30
chips, it controls the external DRAM on the board. The purpose of this
driver is to program memory timing for external memory on the EMC clock
rate change.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Sun, 11 Aug 2019 21:00:35 +0000 (00:00 +0300)]
memory: tegra: Increase handshake timeout on Tegra20
Turned out that it could take over a millisecond under some circumstances,
like running on a very low CPU/memory frequency. TRM says that handshake
happens when there is a "safe" moment, but not explains exactly what that
moment is. Apparently at least memory should be idling and thus the low
frequency should be a reasonable cause for a longer handshake delay.
Dmitry Osipenko [Sun, 11 Aug 2019 21:00:34 +0000 (00:00 +0300)]
memory: tegra: Print a brief info message about EMC timings
During boot print how many memory timings got the driver and what's the
RAM code. This is a very useful information when something is wrong with
boards memory timing.
Suggested-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Sun, 11 Aug 2019 21:00:33 +0000 (00:00 +0300)]
memory: tegra: Pre-configure debug register on Tegra20
The driver expects certain debug features to be disabled in order to
work properly. Let's disable them explicitly for consistency and to not
rely on a boot state.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Sun, 11 Aug 2019 21:00:30 +0000 (00:00 +0300)]
memory: tegra: Don't set EMC rate to maximum on probe for Tegra20
The memory frequency scaling will be managed by tegra20-devfreq driver
and PM QoS once all the prerequisite patches will get upstreamed.
The parent clock is now managed by the clock driver and we also should
assume that PLLM rate can't be changed on some devices (Galaxy Tab 10.1
for example). Altogether there is no point in touching of clock's rate
from the EMC driver.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 15 Feb 2019 15:28:19 +0000 (16:28 +0100)]
memory: tegra: Set DMA mask based on supported address bits
The memory controller on Tegra124 and later supports 34 or more address
bits. Advertise that by setting the DMA mask based on the number of the
address bits.
A proper External Memory Controller clock rounding and parent selection
functionality is required by the EMC drivers, it is not available using
the generic clock implementation because only the Memory Controller driver
is aware of what clock rates are actually available for a particular
device. EMC drivers will have to register a Tegra-specific CLK-API
callback which will perform rounding of a requested rate. EMC clock users
won't be able to request EMC clock by getting -EPROBE_DEFER until EMC
driver is probed and the callback is set up.
The functionality is somewhat similar to the clk-emc.c which serves
Tegra124+ SoCs. The later HW generations support more parent clock sources
and the HW configuration / integration with the EMC drivers differs a tad
from the older gens, hence it's not really worth to try to squash
everything into a single source file.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* tag 'amlogic-drivers' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
soc: amlogic: meson-gx-socinfo: Fix S905D3 ID for VIM3L
soc: amlogic: meson-gx-socinfo: Add S905X3 ID for VIM3L
soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs
firmware: meson_sm: use %*ph to print small buffer
firmware: meson_sm: Rework driver as a proper platform driver
nvmem: meson-efuse: bindings: Add secure-monitor phandle
firmware: meson_sm: Mark chip struct as static const
Olof Johansson [Fri, 8 Nov 2019 18:27:55 +0000 (10:27 -0800)]
Merge tag 'zynqmp-soc-for-v5.5' of https://github.com/Xilinx/linux-xlnx into arm/drivers
arm64: soc: Xilinx SoC changes for v5.5
- Extend firmware interface to cover Versal chip
* tag 'zynqmp-soc-for-v5.5' of https://github.com/Xilinx/linux-xlnx:
firmware: xilinx: Add support for versal soc
dt-bindings: firmware: Add bindings for Versal firmware
soc: xilinx: Set CAP_UNUSABLE requirement for versal while powering down domain
Weiyi Lu [Wed, 28 Aug 2019 09:11:39 +0000 (17:11 +0800)]
soc: mediatek: Refactor sram control
Put sram enable and disable control in separate functions.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
[mb: fix coding style of reading register and changing the read value] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Change from v1: use 0xf0 mask instead of 0xf2 as advised by Neil Armstrong.
Fixes: 1d7c541b8a5b ("soc: amlogic: meson-gx-socinfo: Add S905X3 ID for VIM3L") Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Olof Johansson [Wed, 6 Nov 2019 15:46:02 +0000 (07:46 -0800)]
Merge tag 'imx-drivers-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.5:
- Skip return check for those SCU firmware APIs that are defined as
void function in firmware.
- Use established serial_number attribute instead of custom one to show
SoC's unique ID for i.MX8 SoC drivers.
- Read i.MX8MQ SOC revision from TF-A which parses ROM and exposes the
value through a SMC call. This improves the situation that SOC
revision reports 'unknown' on some older revisions.
- Add a check and warn on unexpected SCU RX to avoid potential stack
corruption in imx-scu driver.
- Fix a sparse warning in imx-scu-irq driver by adding missing header.
- Remove an unneeded call to devm_of_platform_populate() from imx-dsp
driver.
* tag 'imx-drivers-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx8mq: Read SOC revision from TF-A
soc: imx-scu: Using existing serial_number instead of UID
soc: imx8: Using existing serial_number instead of UID
firmware: imx: add missing include of <linux/firmware/imx/sci.h>
firmware: imx: Remove call to devm_of_platform_populate
firmware: imx: Skip return value check for some special SCU firmware APIs
firmware: imx: warn on unexpected RX
Olof Johansson [Wed, 6 Nov 2019 15:45:06 +0000 (07:45 -0800)]
Merge tag 'samsung-drivers-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers
Samsung soc drivers changes for v5.5
1. Minor fixes to Exynos Chipid driver.
2. Add Exynos Adaptive Supply Voltage driver allowing to adjust voltages
used during CPU frequency scaling based on revision of SoC. This
also pulls dependency from PM/OPP tree - driver uses newly added
dev_pm_opp_adjust_voltage() function.
* tag 'samsung-drivers-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
soc: samsung: exynos-asv: Potential NULL dereference in exynos_asv_update_opps()
soc: samsung: chipid: Drop "syscon" compatible requirement
soc: samsung: Add Exynos Adaptive Supply Voltage driver
PM / OPP: Support adjusting OPP voltages at runtime
soc: samsung: chipid: Make exynos_chipid_early_init() static
John Garry [Mon, 4 Nov 2019 17:22:19 +0000 (01:22 +0800)]
logic_pio: Build into a library
Object file logic_pio.o is always built.
Ideally the object file should only be built when required. This is
tricky, as that would be for archs which define PCI_IOBASE, but no common
config option exists for that.
For now, continue to always build but at least ensure the symbols are not
included in the vmlinux when not referenced.
John Garry [Mon, 4 Nov 2019 17:22:16 +0000 (01:22 +0800)]
logic_pio: Define PIO_INDIRECT_SIZE for !CONFIG_INDIRECT_PIO
With the goal of expanding the test coverage of the HiSi LPC driver to
!ARM64, define a dummy PIO_INDIRECT_SIZE for !CONFIG_INDIRECT_PIO, which
is required by the named driver.
Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
John Garry [Mon, 4 Nov 2019 17:22:15 +0000 (01:22 +0800)]
lib: logic_pio: Enforce LOGIC_PIO_INDIRECT region ops are set at registration
Since the only LOGIC_PIO_INDIRECT host (hisi-lpc) now sets the ops prior
to registration, enforce this check for accessors ops at registration
instead of in the IO port accessors to simplify and marginally optimise
the code.
Leonard Crestez [Tue, 29 Oct 2019 23:17:39 +0000 (01:17 +0200)]
soc: imx8mq: Read SOC revision from TF-A
SOC revision on older imx8mq is not available in fuses so on anything
other than B1 current code just reports "unknown".
TF-A already handles this by parsing the ROM and exposes the value
through a SMC call. Call this instead of reimplementing the workaround
in the kernel itself.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Olof Johansson [Mon, 4 Nov 2019 01:25:45 +0000 (17:25 -0800)]
Merge tag 'tegra-for-5.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
soc/tegra: Changes for v5.5-rc1
Adds wake event support on Tegra210, implements the NVMEM API for the
Tegra FUSE block and adds coupled regulators support for Tegra20 and
Tegra30.
* tag 'tegra-for-5.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: pmc: Remove unnecessary memory barrier
soc/tegra: pmc: Query PCLK clock rate at probe time
soc/tegra: regulators: Add regulators coupler for Tegra30
soc/tegra: regulators: Add regulators coupler for Tegra20
soc/tegra: pmc: Configure deep sleep control settings
soc/tegra: pmc: Configure core power request polarity
soc/tegra: pmc: Add wake event support on Tegra210
soc/tegra: pmc: Support wake events on more Tegra SoCs
soc/tegra: fuse: Register cell lookups for compatibility
soc/tegra: fuse: Add cell information
soc/tegra: fuse: Implement nvmem device
soc/tegra: fuse: Restore base on sysfs failure
soc/tegra: pmc: Fix crashes for hierarchical interrupts
soc/tegra: fuse: Add FUSE clock check in tegra_fuse_readl()
Olof Johansson [Mon, 4 Nov 2019 00:53:07 +0000 (16:53 -0800)]
Merge branch 'for_5.5/driver-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/drivers
* 'for_5.5/driver-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
memory: emif: remove set but not used variables 'cs1_used' and 'custom_configs'
soc: ti: omap-prm: fix return value check in omap_prm_probe()
soc: ti: omap-prm: add omap5 PRM data
soc: ti: omap-prm: add am4 PRM data
soc: ti: omap-prm: add dra7 PRM data
soc: ti: omap-prm: add data for am33xx
soc: ti: omap-prm: add omap4 PRM data
soc: ti: omap-prm: add support for denying idle for reset clockdomain
soc: ti: omap-prm: poll for reset complete during de-assert
soc: ti: add initial PRM driver with reset control support
dt-bindings: omap: add new binding for PRM instances
Add support for the power areas in the Renesas R-Car M3-W+ (R8A77961)
SoC to the R-Car System Controller driver.
R-Car M3-W+ (aka R-Car M3-W ES3.0) is very similar to R-Car
M3-W (R8A77960), which allows for both SoCs to share a driver:
- R-Car M3-W+ lacks the A2VC power area, so its area must be
nullified,
- The existing support for the SYSCEXTMASK register added in commit 9bd645af9d2a49ac ("soc: renesas: r8a7796-sysc: Fix power request
conflicts") applies to ES3.0 and later only.
As R-Car M3-W+ uses a different compatible value, differentiate
based on that, instead of on the ES version.
Based on a patch in the BSP by Dien Pham <dien.pham.ry@renesas.com>.
Add support for identifying the R-Car M3-W+ (R8A77961) SoC, which shares
the Product ID Number with R-Car M3-W (R8A77960), but differs in CUT
Number (Ver. 3.0), and uses a different compatible value.
soc: renesas: Add ARCH_R8A77960 for existing R-Car M3-W
Add CONFIG_ARCH_R8A77960 as a new config symbol for R-Car M3-W
(R8A77960), to replace CONFIG_ARCH_R8A7796, and avoid confusion with
R-Car M3-W+ (R8A77961), which will use CONFIG_ARCH_R8A77961.
Note that for now, CONFIG_ARCH_R8A7796 is retained, and just selects
CONFIG_ARCH_R8A77960. This relaxes dependencies of other subsystems on
the SoC configuration symbol, and provides a smooth transition path for
config files through "make oldconfig".
soc: renesas: Rename SYSC_R8A7796 to SYSC_R8A77960
Rename CONFIG_SYSC_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_SYSC_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_SYSC_R8A77961.
Rename r8a7796_sysc_info and r8a7796_sysc_init for consistency.
soc: renesas: Add missing check for non-zero product register address
If the DTB for a device with an RZ/A2 SoC lacks a device node for the
BSID register, the ID validation code falls back to using a register at
address 0x0, which leads to undefined behavior (e.g. reading back a
random value).
This could be fixed by letting fam_rza2.reg point to the actual BSID
register. However, the hardcoded fallbacks were meant for backwards
compatibility with old DTBs only, not for new SoCs. Hence fix this by
validating renesas_family.reg before using it.
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
M3-W+ (R8A77961) SoC, as listed in Table 8.2b ("List of Clocks [R-Car
M3-W/R-Car M3-W+]") of the R-Car Series, 3rd Generation Hardware User's
Manual (Rev. 2.00, Jul. 31, 2019). A gap is added for CSIREF, to
preserve compatibility with the definitions for R-Car M3-W (R8A77960).
Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, SSPSRC, and POST2)
are not included, as they are used as internal clock sources only, and
never referenced from DT.
Dan Carpenter [Tue, 29 Oct 2019 18:27:42 +0000 (21:27 +0300)]
soc: samsung: exynos-asv: Potential NULL dereference in exynos_asv_update_opps()
The dev_pm_opp_get_opp_table() returns error pointers if it's disabled
in the config and it returns NULL if there is an error. This code only
checks for error pointers so it could lead to an Oops inside the
dev_pm_opp_put_opp_table() function.
Fixes: 5ea428595cc5 ("soc: samsung: Add Exynos Adaptive Supply Voltage driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
YueHaibing [Tue, 29 Oct 2019 16:57:57 +0000 (09:57 -0700)]
memory: emif: remove set but not used variables 'cs1_used' and 'custom_configs'
drivers/memory/emif.c:1616:9: warning:
variable cs1_used set but not used [-Wunused-but-set-variable]
drivers/memory/emif.c:1624:36: warning:
variable custom_configs set but not used [-Wunused-but-set-variable]
Wei Yongjun [Tue, 29 Oct 2019 16:57:56 +0000 (09:57 -0700)]
soc: ti: omap-prm: fix return value check in omap_prm_probe()
In case of error, the function devm_ioremap_resource() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check should
be replaced with IS_ERR().
Fixes: 3e99cb214f03 ("soc: ti: add initial PRM driver with reset control support") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
The removed barrier isn't needed because writes/reads are strictly ordered
and even if PMC had separate ports for writes, it wouldn't matter since
the hardware logic takes into effect after triggering CPU's power-gating
and at that point all CPU accesses are guaranteed to be completed. That
barrier was copied from the old arch/ code during transition to the soc/
PMC driver and even that the code structure was different back then, the
barrier didn't have a real useful purpose from the start. Lastly, the
tegra_pmc_writel() naturally inserts wmb() because it uses writel(),
and thus this change doesn't actually make any difference in terms of
interacting with hardware. Hence let's remove the barrier to clean up
code a tad.
soc/tegra: pmc: Query PCLK clock rate at probe time
It is possible to get a lockup if kernel decides to enter LP2 cpuidle
from some clk-notifier, in that case CCF's "prepare" mutex is kept locked
and thus clk_get_rate(pclk) blocks on the same mutex with interrupts being
disabled, hanging machine.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
soc/tegra: regulators: Add regulators coupler for Tegra30
Add regulators coupler for Tegra30 SoCs that performs voltage balancing
of a coupled regulators and thus provides voltage scaling functionality.
There are 2 coupled regulators on all Tegra30 SoCs: CORE and CPU. The
coupled regulator voltages shall be in a range of 300mV from each other
and CORE voltage shall be higher than the CPU by N mV, where N depends
on the CPU voltage.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
soc/tegra: regulators: Add regulators coupler for Tegra20
Add regulators coupler for Tegra20 SoCs that performs voltage balancing
of a coupled regulators and thus provides voltage scaling functionality.
There are 3 coupled regulators on all Tegra20 SoCs: CORE, RTC and CPU.
The CORE and RTC voltages shall be in range of 170mV from each other and
they both shall be higher than the CPU voltage by at least 120mV. This
sounds like it could be handle by a generic voltage balancer, but the CORE
voltage scaling isn't implemented in any of the upstream drivers yet.
It will take quite some time and effort to hook up voltage scaling for
all of the drivers, hence we will use a custom coupler that will manage
the CPU voltage scaling for the starter.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
soc/tegra: pmc: Configure deep sleep control settings
Tegra210 and prior Tegra chips have deep sleep entry and wakeup related
timings which are platform specific that should be configured before
entering into deep sleep.
Below are the timing specific configurations for deep sleep entry and
wakeup.
- Core rail power-on stabilization timer
- OSC clock stabilization timer after SOC rail power is stabilized.
- Core power off time is the minimum wake delay to keep the system
in deep sleep state irrespective of any quick wake event.
These values depends on the discharge time of regulators and turn OFF
time of the PMIC to allow the complete system to finish entering into
deep sleep state.
These values vary based on the platform design and are specified
through the device tree.
This patch has implementation to configure these timings which are must
to have for proper deep sleep and wakeup operations.
soc/tegra: pmc: Support wake events on more Tegra SoCs
This patch allows to create separate irq_set_wake and irq_set_type
implementations for different Tegra designs PMC that has different
wake models which require difference wake registers and different
programming sequence.
AOWAKE model support is available for Tegra186 and Tegra194 only
and it resides within PMC and supports tiered wake architecture.
Tegra210 and prior Tegra designs uses PMC directly to receive wake
events and coordinate the wake sequence.
soc: samsung: chipid: Drop "syscon" compatible requirement
As we dropped the requirement of "syscon" compatible in the chipid
nodes rework code acquiring the regmap to use device_node_to_regmap()
rather than syscon_node_to_regmap().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
soc: samsung: Add Exynos Adaptive Supply Voltage driver
The Adaptive Supply Voltage (ASV) driver adjusts CPU cluster operating
points depending on exact revision of an SoC retrieved from the CHIPID
block or the OTP memory. This allows for some power saving as for some
CPU clock frequencies we can lower CPU cluster's supply voltage comparing
to safe values common to all the SoC revisions.
This patch adds support for Exynos5422/5800 SoC, it is partially based
on code from https://github.com/hardkernel/linux repository,
branch odroidxu4-4.14.y, files: arch/arm/mach-exynos/exynos5422-asv.[ch].
Tested on Odroid XU3, XU4, XU3 Lite.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Olof Johansson [Mon, 28 Oct 2019 15:51:59 +0000 (08:51 -0700)]
Merge tag 'reset-for-v5.5' of git://git.pengutronix.de/git/pza/linux into arm/drivers
Reset controller updates for v5.5
This tag adds support for Meson SM1 ARB resets, Uniphier Pro5 USB3
resets, the Meson-A1 reset controller, SocFPGA Agilex resets, and
Realtek RTD1195/RTD1295 resets.
It adds some reset controller API keywords for get_maintainers.pl and
makes a few remaining reset_control_ops const. Also included are
a conversion of the Qualcomm device tree bindings to yaml and a few
small kerneldoc improvements.
* tag 'reset-for-v5.5' of git://git.pengutronix.de/git/pza/linux:
reset: document (devm_)reset_control_get_optional variants
reset: improve of_xlate documentation
reset: simple: Add Realtek RTD1195/RTD1295
reset: simple: Keep alphabetical order
MAINTAINERS: add reset controller framework keywords
reset: zynqmp: Make reset_control_ops const
reset: hisilicon: hi3660: Make reset_control_ops const
reset: build simple reset controller driver for Agilex
reset: add support for the Meson-A1 SoC Reset Controller
dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
reset: uniphier-glue: Add Pro5 USB3 support
dt-bindings: reset: pdc: Convert PDC Global bindings to yaml
dt-bindings: reset: aoss: Convert AOSS reset bindings to yaml
reset: Remove copy'n'paste redundancy in the comments
reset: meson-audio-arb: add sm1 support
reset: dt-bindings: meson: update arb bindings for sm1
Anson Huang [Fri, 25 Oct 2019 06:56:23 +0000 (14:56 +0800)]
soc: imx-scu: Using existing serial_number instead of UID
The soc_device_attribute structure already contains a serial_number
attribute to show SoC's unique ID, just use it to show SoC's unique
ID instead of creating a new file called soc_uid.
Anson Huang [Fri, 25 Oct 2019 06:56:22 +0000 (14:56 +0800)]
soc: imx8: Using existing serial_number instead of UID
The soc_device_attribute structure already contains a serial_number
attribute to show SoC's unique ID, just use it to show SoC's unique
ID instead of creating a new file called soc_uid.
firmware: imx: add missing include of <linux/firmware/imx/sci.h>
Include <linux/firmware/imx/sci.h> for the declarations of the
functions exported from this driver. This fixes the following
sparse warnings:
drivers/firmware/imx/imx-scu-irq.c:45:5: warning: symbol 'imx_scu_irq_register_notifier' was not declared. Should it be static?
drivers/firmware/imx/imx-scu-irq.c:52:5: warning: symbol 'imx_scu_irq_unregister_notifier' was not declared. Should it be static?
drivers/firmware/imx/imx-scu-irq.c:97:5: warning: symbol 'imx_scu_irq_group_enable' was not declared. Should it be static?
drivers/firmware/imx/imx-scu-irq.c:130:5: warning: symbol 'imx_scu_enable_general_irq_channel' was not declared. Should it be static?
Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Olof Johansson [Thu, 24 Oct 2019 03:00:48 +0000 (20:00 -0700)]
Merge tag 'arm-soc/for-5.5/drivers' of https://github.com/Broadcom/stblinux into arm/drivers
This pull request contains Broadcom ARM/ARM64/MIPS based SoCs drivers
updates for 5.5, please pull the following:
- Markus updates the DPFE driver so as to support deferring the firmware
loading process until the first sysfs attribute is accessed, in the
process he does a bunch of cleanups and minor fixes
- Florian adds support for the DPFE on 7211 which uses a "new style" API
v2 and makes necessary changes along the way
* tag 'arm-soc/for-5.5/drivers' of https://github.com/Broadcom/stblinux:
memory: brcmstb: dpfe: Fixup API version/commands for 7211
memory: brcmstb: dpfe: Compute checksum at __send_command() time
memory: brcmstb: dpfe: support for deferred firmware download
memory: brcmstb: dpfe: pass *priv as argument to brcmstb_dpfe_download_firmware()
memory: brcmstb: dpfe: move init_data into brcmstb_dpfe_download_firmware()
memory: brcmstb: dpfe: add locking around DCPU enable/disable
memory: brcmstb: dpfe: initialize priv->dev
memory: brcmstb: dpfe: rename struct private_data
Olof Johansson [Wed, 23 Oct 2019 20:18:23 +0000 (13:18 -0700)]
Merge tag 'omap-for-v5.5/ti-sysc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/drivers
Changes for ti-sysc interconnect target module driver for v5.5
A series of changes from Tero Kristo for rpm reset control
driver to deal with the ordering requirements between clocks
and resets, and two changes to deal with quirks for musb otg
device.
* tag 'omap-for-v5.5/ti-sysc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
bus: ti-sysc: Use swsup quirks also for am335x musb
bus: ti-sysc: Handle mstandby quirk and use it for musb
bus: ti-sysc: Fix watchdog quirk handling
bus: ti-sysc: avoid toggling power state of module during probe
bus: ti-sysc: drop the extra hardreset during init
bus: ti-sysc: re-order reset and main clock controls
Stephen Boyd [Wed, 16 Oct 2019 14:57:53 +0000 (16:57 +0200)]
PM / OPP: Support adjusting OPP voltages at runtime
On some SoCs the Adaptive Voltage Scaling (AVS) technique is
employed to optimize the operating voltage of a device. At a
given frequency, the hardware monitors dynamic factors and either
makes a suggestion for how much to adjust a voltage for the
current frequency, or it automatically adjusts the voltage
without software intervention. Add an API to the OPP library for
the former case, so that AVS type devices can update the voltages
for an OPP when the hardware determines the voltage should
change. The assumption is that drivers like CPUfreq or devfreq
will register for the OPP notifiers and adjust the voltage
according to suggestions that AVS makes.
This patch is derived from [1] submitted by Stephen.
[1] https://lore.kernel.org/patchwork/patch/599279/
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Roger Lu <roger.lu@mediatek.com>
[s.nawrocki@samsung.com: added handling of OPP min/max voltage] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Olof Johansson [Tue, 22 Oct 2019 01:52:24 +0000 (18:52 -0700)]
soc: mmp: guard include of asm/cputype.h with CONFIG_ARM{,64}
Since this driver is enabled for COMPILE_TEST, it avoids build error
on x86 allmodconfig:
In file included from /build/drivers/phy/marvell/phy-mmp3-usb.c:12:
/build/include/linux/soc/mmp/cputype.h:5:10: fatal error: asm/cputype.h: No such file or directory
Olof Johansson [Mon, 21 Oct 2019 22:31:06 +0000 (15:31 -0700)]
Merge tag 'mmp-drivers-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp into arm/drivers
ARM: Marvell MMP driver patches for v5.5
This tag includes the MMP3 USB2 PHY driver. The branch is based on
mmp-soc-for-v5.5-2 because the driver depends on changes in MMP SoC
support.
* tag 'mmp-drivers-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp:
MAINTAINERS: phy: add entry for USB PHY drivers on MMP SoCs
phy: Add USB2 PHY driver for Marvell MMP3 SoC
MAINTAINERS: mmp: add Git repository
ARM: mmp: remove MMP3 USB PHY registers from regs-usb.h
ARM: mmp: move cputype.h to include/linux/soc/
ARM: mmp: add SMP support
ARM: mmp: add support for MMP3 SoC
ARM: mmp: define MMP_CHIPID by the means of CIU_REG()
ARM: mmp: DT: convert timer driver to use TIMER_OF_DECLARE
ARM: mmp: map the PGU as well
ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP
ARM: l2c: add definition for FWA in PL310 aux register
Olof Johansson [Mon, 21 Oct 2019 21:50:43 +0000 (14:50 -0700)]
Merge tag 'samsung-drivers-dmc-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers
Samsung DMC driver for v5.5
Add Samsung Dynamic Memory Controller for Exynos5422 which provides
scaling of frequency and voltage of memory controller and DRAM. The
driver allows to reduce energy usage without performance impact.
* tag 'samsung-drivers-dmc-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
memory: samsung: exynos5422-dmc: Add support for interrupt from performance counters
memory: samsung: exynos5422-dmc: Fix kfree() of devm-allocated memory and missing static
memory: samsung: exynos5422-dmc: Fix spelling mistake "counld" -> "could"
memory: Add DMC driver for Exynos5422
memory: Extend of_memory with LPDDR3 support
Olof Johansson [Mon, 21 Oct 2019 21:50:31 +0000 (14:50 -0700)]
Merge tag 'renesas-drivers-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers
Renesas driver updates for v5.5
- Add support for the new RZ/G2N (r8a774b1) SoC,
- Fix System Controller power request conflicts on recent R-Car Gen3
and RZ/G2N SoC variants and revisions,
- Minor cleanups.
* tag 'renesas-drivers-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: rcar-sysc: Add r8a774b1 support
soc: renesas: rcar-sysc: Remove unneeded inclusion of <linux/bug.h>
soc: renesas: r8a774c0-sysc: Fix power request conflicts
soc: renesas: rcar-rst: Add support for RZ/G2N
soc: renesas: Identify RZ/G2N
soc: renesas: Add Renesas R8A774B1 config option
soc: renesas: r8a77990-sysc: Fix power request conflicts
soc: renesas: r8a77980-sysc: Fix power request conflicts
soc: renesas: r8a77970-sysc: Fix power request conflicts
soc: renesas: r8a77965-sysc: Fix power request conflicts
soc: renesas: r8a7796-sysc: Fix power request conflicts
soc: renesas: r8a7795-sysc: Fix power request conflicts
soc: renesas: rcar-sysc: Prepare for fixing power request conflicts
dt-bindings: clk: Add r8a774b1 CPG Core Clock Definitions
dt-bindings: power: Add r8a774b1 SYSC power domain definitions
Florian Fainelli [Tue, 15 Oct 2019 22:45:13 +0000 (15:45 -0700)]
memory: brcmstb: dpfe: Fixup API version/commands for 7211
7211 uses a newer version of API v2 which is half way between what was
defined as API v3 and what used to be called API v2 but was used with
DPFE firmwares with major versions 1.x.x.x. Starting with **the new**
API v2, we are no longer getting loadable firmware images, so the
capability to load it is removed (like v3).
To avoid spreading more confusion, map 7268/7271/7278 to the old DPFE
API version 2, 7211 to the new API v2 and introduce the specific
commands for that, and leave newer versions to map to API v3.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Markus Mayer <mmayer@broadcom.com>
Florian Fainelli [Tue, 15 Oct 2019 22:45:12 +0000 (15:45 -0700)]
memory: brcmstb: dpfe: Compute checksum at __send_command() time
Instead of pre-computing the checksum, do it at the time we send the
command, this reduces the possibility of introducing errors as well as
limits the amount of code necessary while adding new commands and/or new
API versions. The MSG_CHKSUM enumeration value is no longer necessary
and is removed.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Markus Mayer <mmayer@broadcom.com>
Markus Mayer [Tue, 15 Oct 2019 22:45:11 +0000 (15:45 -0700)]
memory: brcmstb: dpfe: support for deferred firmware download
We add support for deferred downloading of the DPFE firmware. It may be
necessary to do this if the root file system containing the firmware
image is not yet available at the time the driver's probe function is
being called.
Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Markus Mayer [Tue, 15 Oct 2019 22:45:10 +0000 (15:45 -0700)]
memory: brcmstb: dpfe: pass *priv as argument to brcmstb_dpfe_download_firmware()
Rather than passing a (struct platform_device *) to
brcmstb_dpfe_download_firmware(), we pass a (struct private_data *).
This is the more sensible thing to do.
Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Markus Mayer [Tue, 15 Oct 2019 22:45:09 +0000 (15:45 -0700)]
memory: brcmstb: dpfe: move init_data into brcmstb_dpfe_download_firmware()
Rather than declaring our init_data in several places and passing it as
parameter into brcmstb_dpfe_download_firmware(), we declare it inside
brcmstb_dpfe_download_firmware() instead.
Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Markus Mayer [Tue, 15 Oct 2019 22:45:07 +0000 (15:45 -0700)]
memory: brcmstb: dpfe: initialize priv->dev
Add missing initialization of priv->dev. It is only used in an
emergency error message that is very unlikely to ever occur, which is
how this has remained unnoticed.
Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
projects / linux.git / log