Bjorn Helgaas [Tue, 21 Feb 2017 21:14:18 +0000 (15:14 -0600)]
Merge branch 'pci/host-hisi' into next
* pci/host-hisi:
PCI: generic: Call pci_fixup_irqs() only on ARM
PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports
PCI: hisi: Rename config space accessors to remove "acpi"
PCI: hisi: Add DT almost-ECAM support for Hip06/Hip07 host controllers
PCI: hisi: Use of_device_get_match_data() to simplify probe
Bjorn Helgaas [Tue, 21 Feb 2017 21:13:30 +0000 (15:13 -0600)]
Merge branch 'pci/host-exynos' into next
* pci/host-exynos:
PCI: exynos: Support the PHY generic framework
Documentation: binding: Modify the exynos5440 PCIe binding
phy: phy-exynos-pcie: Add support for Exynos PCIe PHY
Documentation: samsung-phy: Add exynos-pcie-phy binding
PCI: exynos: Refactor to make it easier to support other SoCs
PCI: exynos: Remove duplicated code
PCI: exynos: Use the bitops BIT() macro to build bitmasks
PCI: exynos: Remove unnecessary local variables
PCI: exynos: Replace the *_blk/*_phy/*_elb accessors
PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep"
Bjorn Helgaas [Tue, 21 Feb 2017 21:12:18 +0000 (15:12 -0600)]
Merge branch 'pci/host-designware' into next
* pci/host-designware:
PCI: dwc: Remove dependency of designware on CONFIG_PCI
PCI: dwc: Add CONFIG_PCIE_DW_HOST to enable PCI dwc host
PCI: dwc: Split pcie-designware.c into host and core files
PCI: dwc: designware: Fix style errors in pcie-designware.c
PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc()
PCI: dwc: all: Split struct pcie_port into host-only and core structures
PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init()
PCI: dwc: all: Rename cfg_read/cfg_write to read/write
PCI: dwc: all: Use platform_set_drvdata() to save private data
PCI: dwc: designware: Move register defines to designware header file
PCI: dwc: Use PTR_ERR_OR_ZERO to simplify code
PCI: dra7xx: Group PHY API invocations
PCI: dra7xx: Enable MSI and legacy interrupts simultaneously
PCI: dra7xx: Add support to force RC to work in GEN1 mode
PCI: dra7xx: Simplify probe code with devm_gpiod_get_optional()
PCI: Move DesignWare IP support to new drivers/pci/dwc/ directory
PCI: designware: Check for iATU unroll only on platforms that use ATU
PCI: dwc: Remove dependency of designware on CONFIG_PCI
CONFIG_PCI is used to enable host mode PCI. In preparation for adding
endpoint mode support to designware driver, remove the dependency of
designware on CONFIG_PCI and make only the host-specific part depend on
CONFIG_PCI.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
PCI: dwc: Add CONFIG_PCIE_DW_HOST to enable PCI dwc host
Now that PCI designware host has a separate file, add a new PCIE_DW_HOST
config symbol to select the host-only driver. This will enable to
independently select host support and endpoint support (when it's added).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
PCI: dwc: Split pcie-designware.c into host and core files
Split pcie-designware.c into pcie-designware-host.c that contains the host
specific parts of the driver and pcie-designware.c that contains the parts
used by both host driver and endpoint driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc()
The "num-lanes" DT property is parsed in dw_pcie_host_init(). However
num-lanes is applicable to both root complex mode and endpoint mode. As a
first step, move the parsing of this property outside dw_pcie_host_init().
This is in preparation for splitting pcie-designware.c to pcie-designware.c
and pcie-designware-host.c
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
PCI: dwc: all: Split struct pcie_port into host-only and core structures
Keep only the host-specific members in struct pcie_port and move the common
members (i.e common to both host and endpoint) to struct dw_pcie. This is
in preparation for adding endpoint mode support to designware driver.
While at that also fix checkpatch warnings.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Richard Zhu <hongxing.zhu@nxp.com> CC: Lucas Stach <l.stach@pengutronix.de> CC: Murali Karicheri <m-karicheri2@ti.com> CC: Minghuan Lian <minghuan.Lian@freescale.com> CC: Mingkai Hu <mingkai.hu@freescale.com> CC: Roy Zang <tie-fei.zang@freescale.com> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Niklas Cassel <niklas.cassel@axis.com> CC: Jesper Nilsson <jesper.nilsson@axis.com> CC: Joao Pinto <Joao.Pinto@synopsys.com> CC: Zhou Wang <wangzhou1@hisilicon.com> CC: Gabriele Paoloni <gabriele.paoloni@huawei.com> CC: Stanimir Varbanov <svarbanov@mm-sol.com> CC: Pratyush Anand <pratyush.anand@gmail.com>
PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init()
No functional change. Get device pointer at the beginning of
dw_pcie_host_init() instead of getting it all over dw_pcie_host_init().
This is in preparation for splitting struct pcie_port into host and core
structures (once split pcie_port will not have device pointer).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
PCI: dwc: all: Rename cfg_read/cfg_write to read/write
No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do
anything specific to access configuration space. It can be just renamed to
dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-By: Joao Pinto <jpinto@synopsys.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Murali Karicheri <m-karicheri2@ti.com> CC: Stanimir Varbanov <svarbanov@mm-sol.com> CC: Pratyush Anand <pratyush.anand@gmail.com>
PCI: dwc: all: Use platform_set_drvdata() to save private data
Add platform_set_drvdata() in all designware-based drivers to store the
private data structure of the driver so that dev_set_drvdata() can be used
to get back private data structure in add_pcie_port/host_init. This is in
preparation for splitting struct pcie_port into core and host only
structures. After the split pcie_port will not be part of the driver's
private data structure and *container_of* used now to get the private data
pointer cannot be used.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Richard Zhu <hongxing.zhu@nxp.com> CC: Lucas Stach <l.stach@pengutronix.de> CC: Murali Karicheri <m-karicheri2@ti.com> CC: Minghuan Lian <minghuan.Lian@freescale.com> CC: Mingkai Hu <mingkai.hu@freescale.com> CC: Roy Zang <tie-fei.zang@freescale.com> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Niklas Cassel <niklas.cassel@axis.com> CC: Jesper Nilsson <jesper.nilsson@axis.com> CC: Joao Pinto <Joao.Pinto@synopsys.com> CC: Zhou Wang <wangzhou1@hisilicon.com> CC: Gabriele Paoloni <gabriele.paoloni@huawei.com> CC: Stanimir Varbanov <svarbanov@mm-sol.com> CC: Pratyush Anand <pratyush.anand@gmail.com>
PCI: dwc: designware: Move register defines to designware header file
No functional change. Move the register defines and other macros from
pcie-designware.c to pcie-designware.h. This is in preparation to split the
pcie-designware.c file into designware core file and host-specific file.
While at that also fix a checkpatch warning.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-By: Joao Pinto <jpinto@synopsys.com>
Fengguang Wu [Sat, 4 Feb 2017 01:35:32 +0000 (09:35 +0800)]
PCI: dwc: Use PTR_ERR_OR_ZERO to simplify code
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR to avoid the
following warnings found by scripts/coccinelle/api/ptr_ret.cocci:
drivers/pci/dwc/pcie-qcom.c:215:1-3: WARNING: PTR_ERR_OR_ZERO can be used
drivers/pci/dwc/pcie-qcom.c:247:1-3: WARNING: PTR_ERR_OR_ZERO can be used
drivers/pci/dwc/pcie-qcom.c:481:1-3: WARNING: PTR_ERR_OR_ZERO can be used
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Kishon Vijay Abraham I <kishon@ti.com>
No functional change. PHY APIs like phy_init()/phy_power_on() are invoked
from multiple places. Group all the PHY APIs in dra7xx_pcie_enable_phy()
and dra7xx_pcie_disable_phy() and use these functions for enabling or
disabling the PHY.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
PCI: dra7xx: Enable MSI and legacy interrupts simultaneously
pci-dra7xx driver had a bug in that if CONFIG_PCI_MSI config is enabled, it
doesn't support legacy interrupt. Fix it here so that both MSI and legacy
interrupts can be enabled simultaneously and the interrupt mechanism
supported by the endpoint device will be used.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
PCI: dra7xx: Add support to force RC to work in GEN1 mode
PCIe in AM57x/DRA7x devices is by default configured to work in GEN2 mode.
However there may be situations when working in GEN1 mode is desired. One
example is limitation i925 (PCIe GEN2 mode not supported at junction
temperatures < 0C).
Add support to force Root Complex to work in GEN1 mode if so desired, but
don't force GEN1 mode on any board just yet.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
PCI: Move DesignWare IP support to new drivers/pci/dwc/ directory
Group all the PCI drivers that use DesignWare core in dwc directory.
dwc IP is capable of operating in both host mode and device mode and
keeping it inside the *host* directory is misleading.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-By: Joao Pinto <jpinto@synopsys.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Minghuan Lian <minghuan.Lian@freescale.com> Cc: Mingkai Hu <mingkai.hu@freescale.com> Cc: Roy Zang <tie-fei.zang@freescale.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
Jaehoon Chung [Mon, 13 Feb 2017 08:26:12 +0000 (17:26 +0900)]
Documentation: binding: Modify the exynos5440 PCIe binding
According to using PHY framework, updates the exynos5440-pcie binding. For
maintaining backward compatibility, leaves the current dt-binding. (It
should be deprecated.)
Recommends to use the PHY Framework and "config" property to follow the
designware-pcie binding. If you use the old way, can see "missing *config*
reg space" message. Because the getting configuration space address from
range is old way.
NOTE: When use the "config" property, first name of 'reg-names' must be set
to "elbi". Otherwise driver can't maintain the backward capability.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Rob Herring <robh@kernel.org>
Jaehoon Chung [Mon, 13 Feb 2017 08:26:11 +0000 (17:26 +0900)]
phy: phy-exynos-pcie: Add support for Exynos PCIe PHY
Add support for Generic PHY framework about Exynos SoCs. Current Exynos
PCIe driver doesn't use the PHY framework, which makes it difficult to
upstream the other Exynos variants because of different PHY registers.
Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe
driver.
[bhelgaas: depend on "OF && (ARCH_EXYNOS || COMPILE_TEST)", update
copyright year, both per Vivek] Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Jingoo Han <jingoohan1@gmail.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Haiyang Zhang [Mon, 13 Feb 2017 18:10:11 +0000 (18:10 +0000)]
PCI: hv: Use device serial number as PCI domain
Use the device serial number as the PCI domain. The serial numbers start
with 1 and are unique within a VM. So names, such as VF NIC names, that
include domain number as part of the name, can be shorter than that based
on part of bus UUID previously. The new names will also stay same for VMs
created with copied VHD and same number of devices.
Signed-off-by: Haiyang Zhang <haiyangz@microsoft.com> Signed-off-by: Stephen Hemminger <sthemmin@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com>
Bjorn Helgaas [Wed, 15 Feb 2017 17:56:10 +0000 (11:56 -0600)]
Merge branch 'pci/msi' into next
* pci/msi:
PCI/MSI: Update MSI/MSI-X bits in PCIEBUS-HOWTO
PCI/MSI: Document pci_alloc_irq_vectors(), deprecate pci_enable_msi()
PCI/MSI: Return -ENOSPC if pci_enable_msi_range() can't get enough vectors
PCI/portdrv: Use pci_irq_alloc_vectors()
PCI/MSI: Check that we have a legacy interrupt line before using it
PCI/MSI: Remove pci_msi_domain_{alloc,free}_irqs()
PCI/MSI: Remove unused pci_msi_create_default_irq_domain()
PCI/MSI: Return failure when msix_setup_entries() fails
PCI/MSI: Remove pci_enable_msi_{exact,range}()
amd-xgbe: Update PCI support to use new IRQ functions
[media] cobalt: use pci_irq_allocate_vectors()
PCI/MSI: Fix msi_capability_init() kernel-doc warnings
Bjorn Helgaas [Wed, 15 Feb 2017 17:56:08 +0000 (11:56 -0600)]
Merge branch 'pci/enumeration' into next
* pci/enumeration:
PCI: Remove duplicate check for positive return value from probe() functions
PCI: Enable PCIe Extended Tags if supported
PCI: Avoid possible deadlock on pci_lock and p->pi_lock
PCI/ACPI: Fix bus range comparison in pci_mcfg_lookup()
PCI: Apply _HPX settings only to relevant devices
Bjorn Helgaas [Wed, 15 Feb 2017 17:56:07 +0000 (11:56 -0600)]
Merge branch 'pci/aspm' into next
* pci/aspm:
PCI/ASPM: Add comment about L1 substate latency
PCI/ASPM: Configure L1 substate settings
PCI/ASPM: Calculate and save the L1.2 timing parameters
PCI/ASPM: Read and set up L1 substate capabilities
PCI/ASPM: Add support for L1 substates
PCI/ASPM: Add L1 substate capability structure register definitions
Update the MSI/MSI-X bits in PCIEBUS-HOWTO. Stop talking about low-level
details that mention deprecated APIs and concentrate on what service
drivers should do and why.
Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Rajat Jain [Tue, 3 Jan 2017 06:34:15 +0000 (22:34 -0800)]
PCI/ASPM: Add comment about L1 substate latency
Since the exit latencies for L1 substates are not advertised by a device,
it is not clear in spec how to do a L1 substate exit latency check. We
assume that the L1 exit latencies advertised by a device include L1
substate latencies (and hence do not do any check). If that is not true,
we should do some sort of check here.
(I'm not clear about what that check should like currently. I'd be glad to
take up any suggestions).
Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Rajat Jain [Tue, 3 Jan 2017 06:34:11 +0000 (22:34 -0800)]
PCI/ASPM: Add support for L1 substates
Add support for ASPM L1 substates. For details about L1 substates, see the
PCIe r3.1 spec, which includes the ECN below in secs 5.5 and 7.33.
Add macros for the 4 new L1 substates, and add a new ASPM "POWER_SUPERSAVE"
policy that can be used to enable L1 substates on a system if desired. The
new policy is in a sense, a superset of the existing POWERSAVE policy. The
4 policies are now:
DEFAULT: Reads and uses whatever ASPM states BIOS enabled
PERFORMANCE: Everything except L0 disabled.
POWERSAVE: L0s and L1 enabled (but not L1 substates)
POWER_SUPERSAVE: L0s + L1 + L1 substates also enabled
Niyas Ahmed S T [Wed, 1 Feb 2017 04:43:06 +0000 (10:13 +0530)]
PCI: exynos: Refactor to make it easier to support other SoCs
Currently the Exynos PCIe driver only supports the Exynos5440 SoC.
Refactor the driver to allow support for other Exynos SoC.
Following are the main changes in this patch:
1) Add separate structs for memory, clock resources
Future Exynos SoC will have different hardware resources such as iomem,
clocks, regmap handles, etc., so keeping these resources in separate
structs will let us initialize them via per-SoC ops and avoid littering
the code with of_machine_is_compatible().
2) Add exynos_pcie_ops struct which will allow us to support the
differences in resources in different Exynos SoC.
No functional change intended.
Signed-off-by: Niyas Ahmed S T <niyas.ahmed@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Jingoo Han <jingoohan1@gmail.com>
Dennis Chen [Thu, 1 Dec 2016 02:15:04 +0000 (10:15 +0800)]
PCI/MSI: Return -ENOSPC if pci_enable_msi_range() can't get enough vectors
If device doesn't support as many MSI vectors as the driver requested, we
previously returned -EINVAL from __pci_enable_msi_range() and
pci_enable_msi_range(). In other similar situations in both
__pci_enable_msi_range() and __pci_enable_msix_range(), we returned
-ENOSPC.
Return -ENOSPC from __pci_enable_msi_range() so we do it consistently.
[bhelgaas: changelog] Signed-off-by: Dennis Chen <dennis.chen@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Tejun Heo <tj@kernel.org> CC: Christoph Hellwig <hch@lst.de> CC: Tom Long Nguyen <tom.l.nguyen@intel.com> CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org> CC: Marc Zyngier <marc.zyngier@arm.com> CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> CC: Steve Capper <steve.capper@arm.com>
PCI/MSI: Check that we have a legacy interrupt line before using it
It seems like there are some devices (e.g. the PCIe root port driver) that
may not always have a INTx interrupt. Check for dev->irq before returning
a legacy interrupt in pci_irq_alloc_vectors to properly handle this case.
Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Dexuan Cui [Fri, 10 Feb 2017 21:18:46 +0000 (15:18 -0600)]
PCI: hv: Fix wslot_to_devfn() to fix warnings on device removal
The devfn of 00:02.0 is 0x10. devfn_to_wslot(0x10) == 0x2, and
wslot_to_devfn(0x2) should be 0x10, while it's 0x2 in the current code.
Due to this, hv_eject_device_work() -> pci_get_domain_bus_and_slot()
returns NULL and pci_stop_and_remove_bus_device() is not called.
Later when the real device driver's .remove() is invoked by
hv_pci_remove() -> pci_stop_root_bus(), some warnings can be noticed
because the VM has lost the access to the underlying device at that
time.
Signed-off-by: Jake Oshins <jakeo@microsoft.com> Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Haiyang Zhang <haiyangz@microsoft.com> CC: stable@vger.kernel.org CC: K. Y. Srinivasan <kys@microsoft.com> CC: Stephen Hemminger <sthemmin@microsoft.com>
PCI: Remove duplicate check for positive return value from probe() functions
Function __pci_device_probe() tries to be careful about a PCI driver
probe() hook returning a positive value, but this is not really necessary,
since the same fix up is already done in local_pci_probe() (preceded by a
noisy warning), which renders this instance dead code.
Signed-off-by: Gabriel Krisman Bertazi <krisman@collabora.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Sinan Kaya [Fri, 20 Jan 2017 14:16:51 +0000 (09:16 -0500)]
PCI: Enable PCIe Extended Tags if supported
Every PCIe device can generate 5-bit transaction Tags, which allow up to 32
concurrent requests. Some devices can generate 8-bit Extended Tags, which
allow up to 256 concurrent requests.
Per the ECN mentioned below, all PCIe Receivers are expected to support
Extended Tags, so devices are allowed (but not required) to enable them by
default.
If a device supports Extended Tags but does not enable them by default,
enable them. This allows the device to have up to 256 outstanding
transactions at a time, which may improve performance.
No hardware seems to actually call .link_reset(), and no driver implements
it as more than a nop stub.
Drop mentions of the callback from everywhere. It's dropped from the
documentation as well, but the doc really needs to be updated to reflect
reality better (e.g., on PCIe, slot reset is the link reset). This will be
done in a later patch.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Dongdong Liu [Thu, 12 Jan 2017 06:28:24 +0000 (14:28 +0800)]
PCI: generic: Call pci_fixup_irqs() only on ARM
pci_fixup_irqs() is problematic because:
- it's called when we enumerate a host bridge, so we don't fixup IRQs for
hot-added PCI devices, and
- it fixes up IRQs for all PCI devices in the system, so if we call it
multiple times, e.g., if we have several host controllers, we may
reallocate an IRQ for a device after a driver has already claimed it.
We plan to replace pci_fixup_irqs() soon, but we still need it on ARM
because we don't have any other generic method for doing this.
On ARM64, we don't need pci_fixup_irqs() because we do IRQ setup when we
bind a driver to the device (in the pci_device_probe() ->
pcibios_alloc_irq() path).
pci-host-common.c is currently only used on ARM and ARM64. In principle,
it could be used on x86, and we wouldn't want pci_fixup_irqs() there
either, because x86 does IRQ setup in the pci_enable_device() path.
[bhelgaas: changelog, use #ifdef ARM, not #ifndef ARM64] Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Dongdong Liu [Fri, 3 Feb 2017 21:02:07 +0000 (15:02 -0600)]
PCI: Disable MSI for HiSilicon Hip06/Hip07 Root Ports
The PCIe Root Port in Hip06/Hip07 SoCs advertises an MSI capability, but it
cannot generate MSIs. It can transfer MSI/MSI-X from downstream devices,
but does not support MSI/MSI-X itself.
Add a quirk to prevent use of MSI/MSI-X by the Root Port.
[bhelgaas: changelog, sort vendor ID #define, drop device ID #define] Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com>
Bjorn Helgaas [Tue, 7 Feb 2017 14:41:09 +0000 (08:41 -0600)]
PCI: hisi: Rename config space accessors to remove "acpi"
There's nothing ACPI-specific about the config space accessors
hisi_pcie_acpi_rd_conf() and hisi_pcie_acpi_wr_conf(), and they're used for
both the ACPI and the DT driver model.
Rename them to hisi_pcie_rd_conf() and hisi_pcie_wr_conf(). No functional
change intended.
Jaehoon Chung [Mon, 16 Jan 2017 06:31:36 +0000 (15:31 +0900)]
PCI: exynos: Remove unnecessary local variables
Remove unnecessary local variables: elbi_base, phy_base, block_base. We
need one resource structure for assigning each resource. Reuse the single
'res' variable for all.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Jingoo Han <jingoohan1@gmail.com>
Dongdong Liu [Mon, 6 Feb 2017 06:25:04 +0000 (14:25 +0800)]
PCI: hisi: Add DT almost-ECAM support for Hip06/Hip07 host controllers
The PCIe controller in HiSilicon Hip06/Hip07 SoCs is not completely
ECAM-compliant. It is non-ECAM only for the RC bus config space; for any
other bus underneath the root bus it does support ECAM access.
Add DT support for the almost-ECAM Hip06/Hip07 controllers.
[bhelgaas: drop dev->of_node test, driver name "hisi-pcie-almost-ecam"] Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com>
Matthew R. Ochs [Tue, 29 Nov 2016 18:00:40 +0000 (12:00 -0600)]
PCI: Increase VPD access timeout to 125ms
The PCI core uses a fixed 50ms timeout when waiting for VPD accesses to
complete. When an access does not complete within this period, a warning
is logged and an error returned to the caller.
While this default timeout is valid for most hardware, some devices can
experience longer access delays under certain circumstances. For example,
one of the IBM CXL Flash devices can take up to ~120ms in a worst-case
scenario. These types of devices can benefit from an extended timeout.
To support devices with a longer access delay, increase the timeout in
pci_vpd_wait() to 125ms. The PCI specification is silent with respect to
VPD delays, therefore there is no concern for violating a threshold.
Tested-by: Uma Krishnan <ukrishn@linux.vnet.ibm.com> Signed-off-by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Bjorn Helgaas [Sat, 14 Jan 2017 00:05:12 +0000 (18:05 -0600)]
PCI: Avoid possible deadlock on pci_lock and p->pi_lock
pci_lock is an IRQ-safe spinlock that protects all accesses to PCI
configuration space (see PCI_OP_READ() and PCI_OP_WRITE() in pci/access.c).
The pci_cfg_access_unlock() path acquires pci_lock, then p->pi_lock (inside
wake_up_all()). According to lockdep, there is a possible path involving
snbep_uncore_pci_read_counter() that could acquire them in the reverse
order: acquiring p->pi_lock, then pci_lock, which could result in a
deadlock. Lockdep details are in the bugzilla below.
Avoid the possible deadlock by dropping pci_lock before waking up any
config access waiters.
Alex Williamson [Thu, 19 Jan 2017 15:51:30 +0000 (08:51 -0700)]
PCI: Add ACS quirk for Intel Union Point
Intel 200-series chipsets have the same errata as 100-series: the ACS
capability doesn't follow the PCIe spec, the capability and control
registers are dwords rather than words. Add PCIe root port device IDs to
existing quirk.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
All multi-MSI allocations are now done through pci_irq_alloc_vectors(), so
remove the old pci_enable_msi_range() and pci_enable_msi_exact()
interfaces.
Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tom Lendacky [Fri, 13 Jan 2017 08:05:53 +0000 (09:05 +0100)]
amd-xgbe: Update PCI support to use new IRQ functions
Some of the PCI MSI/MSI-X functions have been deprecated and it is
recommended to use the new pci_alloc_irq_vectors() function. Convert the
code over to use the new function. Also, modify the way in which the IRQs
are requested - try for multiple MSI-X/MSI first, then a single MSI/legacy
interrupt.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Zhou Wang [Wed, 4 Jan 2017 07:00:06 +0000 (15:00 +0800)]
PCI/ACPI: Fix bus range comparison in pci_mcfg_lookup()
The configuration data provided by an MCFG entry, i.e., PCI segment and bus
range, may span multiple host bridges.
pci_mcfg_lookup() previously required an exact match of the host bridge
starting bus and the MCFG starting bus, which made the following
configuration fail:
MCFG region:
segment: 0
bus range: 0x00-0xff
host bridge
segment: 0
bus range: 0x20-0x4f
Relax the bus range check in pci_mcfg_lookup() so we can use any MCFG entry
that contains the required bus range, as we do in pci_mmconfig_lookup().
[bhelgaas: changelog] Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tomasz Nowicki <tn@semihalf.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
..//drivers/pci/msi.c:623: warning: No description found for parameter 'affd'
..//drivers/pci/msi.c:623: warning: Excess function parameter 'affinity' description in 'msi_capability_init'
Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bhumika Goyal [Mon, 26 Dec 2016 15:36:35 +0000 (21:06 +0530)]
PCI: acpiphp_ibm: Make ibm_apci_table_attr __ro_after_init
ibm_apci_table_attr is not modified after being initialized by
ibm_acpiphp_init(). It is passed as an argument to the functions
sysfs_{remove/create}_bin_file(), but both the arguments are const.
Add __ro_after_init to its declaration.
PCI: designware: Check for iATU unroll only on platforms that use ATU
Previously we checked for iATU unroll support by reading PCIE_ATU_VIEWPORT
even on platforms, e.g., Keystone, that do not have ATU ports. This can
cause bad behavior such as asynchronous external aborts:
OF: PCI: MEM 0x60000000..0x6fffffff -> 0x60000000
Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
pgd = c0003000
[00000000] *pgd=80000800004003, *pmd=00000000
Internal error: : 1211 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.0-00009-g6ff59d2-dirty #7
Hardware name: Keystone
task: eb878000 task.stack: eb866000
PC is at dw_pcie_setup_rc+0x24/0x380
LR is at ks_pcie_host_init+0x10/0x170
Move the dw_pcie_iatu_unroll_enabled() check so we only call it on
platforms that do not use the ATU. These platforms supply their own
->rd_other_conf() and ->wr_other_conf() methods.
[bhelgaas: changelog] Fixes: a0601a470537 ("PCI: designware: Add iATU Unroll feature") Fixes: 416379f9ebde ("PCI: designware: Check for iATU unroll support after initializing host") Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Joao Pinto <jpinto@synopsys.com> CC: stable@vger.kernel.org # v4.9+
Bjorn Helgaas [Mon, 2 Jan 2017 20:04:24 +0000 (14:04 -0600)]
PCI: Apply _HPX settings only to relevant devices
Previously we didn't check the type of device before trying to apply Type 1
(PCI-X) or Type 2 (PCIe) Setting Records from _HPX.
We don't support PCI-X Setting Records, so this was harmless, but the
warning was useless.
We do support PCIe Setting Records, and we didn't check whether a device
was PCIe before applying settings. I don't think anything bad happened on
non-PCIe devices because pcie_capability_clear_and_set_word(),
pcie_cap_has_lnkctl(), etc., would fail before doing any harm. But it's
ugly to depend on those internals.
Check the device type before attempting to apply Type 1 and Type 2 Setting
Records (Type 0 records are applicable to PCI, PCI-X, and PCIe devices).
A side benefit is that this prevents useless "not supported" warnings when
a BIOS supplies a Type 1 (PCI-X) Setting Record and we try to apply it to
every single device:
pci 0000:00:00.0: PCI-X settings not supported
After this patch, we'll get the warning only when a BIOS supplies a Type 1
record and we have a PCI-X device to which it should be applied.
Bjorn Helgaas [Thu, 29 Dec 2016 17:27:52 +0000 (11:27 -0600)]
PCI: Remove res_to_dev_res() debug message
Remove res_to_dev_res() debug message. This is printed from a lookup
function. If the message is important, it should be printed from the
caller with more context.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Yinghai Lu <yinghai@kernel.org>
Larry Finger [Fri, 23 Dec 2016 03:06:53 +0000 (21:06 -0600)]
powerpc: Fix build warning on 32-bit PPC
I am getting the following warning when I build kernel 4.9-git on my
PowerBook G4 with a 32-bit PPC processor:
AS arch/powerpc/kernel/misc_32.o
arch/powerpc/kernel/misc_32.S:299:7: warning: "CONFIG_FSL_BOOKE" is not defined [-Wundef]
This problem is evident after commit 989cea5c14be ("kbuild: prevent
lib-ksyms.o rebuilds"); however, this change in kbuild only exposes an
error that has been in the code since 2005 when this source file was
created. That was with commit 9994a33865f4 ("powerpc: Introduce
entry_{32,64}.S, misc_{32,64}.S, systbl.S").
The offending line does not make a lot of sense. This error does not
seem to cause any errors in the executable, thus I am not recommending
that it be applied to any stable versions.
Thanks to Nicholas Piggin for suggesting this solution.
Fixes: 9994a33865f4 ("powerpc: Introduce entry_{32,64}.S, misc_{32,64}.S, systbl.S") Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sun, 25 Dec 2016 22:56:58 +0000 (14:56 -0800)]
avoid spurious "may be used uninitialized" warning
The timer type simplifications caused a new gcc warning:
drivers/base/power/domain.c: In function ‘genpd_runtime_suspend’:
drivers/base/power/domain.c:562:14: warning: ‘time_start’ may be used uninitialized in this function [-Wmaybe-uninitialized]
elapsed_ns = ktime_to_ns(ktime_sub(ktime_get(), time_start));
despite the actual use of "time_start" not having changed in any way.
It appears that simply changing the type of ktime_t from a union to a
plain scalar type made gcc check the use.
The variable wasn't actually used uninitialized, but gcc apparently
failed to notice that the conditional around the use was exactly the
same as the conditional around the initialization of that variable.
Add an unnecessary initialization just to shut up the compiler.
Linus Torvalds [Sun, 25 Dec 2016 22:30:04 +0000 (14:30 -0800)]
Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer type cleanups from Thomas Gleixner:
"This series does a tree wide cleanup of types related to
timers/timekeeping.
- Get rid of cycles_t and use a plain u64. The type is not really
helpful and caused more confusion than clarity
- Get rid of the ktime union. The union has become useless as we use
the scalar nanoseconds storage unconditionally now. The 32bit
timespec alike storage got removed due to the Y2038 limitations
some time ago.
That leaves the odd union access around for no reason. Clean it up.
Both changes have been done with coccinelle and a small amount of
manual mopping up"
* 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
ktime: Get rid of ktime_equal()
ktime: Cleanup ktime_set() usage
ktime: Get rid of the union
clocksource: Use a plain u64 instead of cycle_t
Linus Torvalds [Sun, 25 Dec 2016 22:05:56 +0000 (14:05 -0800)]
Merge branch 'smp-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull SMP hotplug notifier removal from Thomas Gleixner:
"This is the final cleanup of the hotplug notifier infrastructure. The
series has been reintgrated in the last two days because there came a
new driver using the old infrastructure via the SCSI tree.
Summary:
- convert the last leftover drivers utilizing notifiers
- fixup for a completely broken hotplug user
- prevent setup of already used states
- removal of the notifiers
- treewide cleanup of hotplug state names
- consolidation of state space
There is a sphinx based documentation pending, but that needs review
from the documentation folks"
* 'smp-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/armada-xp: Consolidate hotplug state space
irqchip/gic: Consolidate hotplug state space
coresight/etm3/4x: Consolidate hotplug state space
cpu/hotplug: Cleanup state names
cpu/hotplug: Remove obsolete cpu hotplug register/unregister functions
staging/lustre/libcfs: Convert to hotplug state machine
scsi/bnx2i: Convert to hotplug state machine
scsi/bnx2fc: Convert to hotplug state machine
cpu/hotplug: Prevent overwriting of callbacks
x86/msr: Remove bogus cleanup from the error path
bus: arm-ccn: Prevent hotplug callback leak
perf/x86/intel/cstate: Prevent hotplug callback leak
ARM/imx/mmcd: Fix broken cpu hotplug handling
scsi: qedi: Convert to hotplug state machine
Linus Torvalds [Sun, 25 Dec 2016 22:01:28 +0000 (14:01 -0800)]
Merge branch 'turbostat' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux
Pull turbostat updates from Len Brown.
* 'turbostat' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux:
tools/power turbostat: remove obsolete -M, -m, -C, -c options
tools/power turbostat: Make extensible via the --add parameter
tools/power turbostat: Denverton uses a 25 MHz crystal, not 19.2 MHz
tools/power turbostat: line up headers when -M is used
tools/power turbostat: fix SKX PKG_CSTATE_LIMIT decoding
tools/power turbostat: Support Knights Mill (KNM)
tools/power turbostat: Display HWP OOB status
tools/power turbostat: fix Denverton BCLK
tools/power turbostat: use intel-family.h model strings
tools/power/turbostat: Add Denverton RAPL support
tools/power/turbostat: Add Denverton support
tools/power/turbostat: split core MSR support into status + limit
tools/power turbostat: fix error case overflow read of slm_freq_table[]
tools/power turbostat: Allocate correct amount of fd and irq entries
tools/power turbostat: switch to tab delimited output
tools/power turbostat: Gracefully handle ACPI S3
tools/power turbostat: tidy up output on Joule counter overflow
Nicholas Piggin [Sun, 25 Dec 2016 03:00:30 +0000 (13:00 +1000)]
mm: add PageWaiters indicating tasks are waiting for a page bit
Add a new page flag, PageWaiters, to indicate the page waitqueue has
tasks waiting. This can be tested rather than testing waitqueue_active
which requires another cacheline load.
This bit is always set when the page has tasks on page_waitqueue(page),
and is set and cleared under the waitqueue lock. It may be set when
there are no tasks on the waitqueue, which will cause a harmless extra
wakeup check that will clears the bit.
The generic bit-waitqueue infrastructure is no longer used for pages.
Instead, waitqueues are used directly with a custom key type. The
generic code was not flexible enough to have PageWaiters manipulation
under the waitqueue lock (which simplifies concurrency).
This improves the performance of page lock intensive microbenchmarks by
2-3%.
Putting two bits in the same word opens the opportunity to remove the
memory barrier between clearing the lock bit and testing the waiters
bit, after some work on the arch primitives (e.g., ensuring memory
operand widths match and cover both bits).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Bob Peterson <rpeterso@redhat.com> Cc: Steven Whitehouse <swhiteho@redhat.com> Cc: Andrew Lutomirski <luto@kernel.org> Cc: Andreas Gruenbacher <agruenba@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Mel Gorman <mgorman@techsingularity.net> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Thomas Gleixner [Sun, 25 Dec 2016 11:30:41 +0000 (12:30 +0100)]
ktime: Cleanup ktime_set() usage
ktime_set(S,N) was required for the timespec storage type and is still
useful for situations where a Seconds and Nanoseconds part of a time value
needs to be converted. For anything where the Seconds argument is 0, this
is pointless and can be replaced with a simple assignment.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org>
Thomas Gleixner [Sun, 25 Dec 2016 10:38:40 +0000 (11:38 +0100)]
ktime: Get rid of the union
ktime is a union because the initial implementation stored the time in
scalar nanoseconds on 64 bit machine and in a endianess optimized timespec
variant for 32bit machines. The Y2038 cleanup removed the timespec variant
and switched everything to scalar nanoseconds. The union remained, but
become completely pointless.
Get rid of the union and just keep ktime_t as simple typedef of type s64.
The conversion was done with coccinelle and some manual mopping up.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org>
Thomas Gleixner [Wed, 21 Dec 2016 19:19:57 +0000 (20:19 +0100)]
irqchip/armada-xp: Consolidate hotplug state space
The mpic is either the main interrupt controller or is cascaded behind a
GIC. The mpic is single instance and the modes are mutually exclusive, so
there is no reason to have seperate cpu hotplug states.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Sebastian Siewior <bigeasy@linutronix.de> Cc: Marc Zyngier <marc.zyngier@arm.com> Link: http://lkml.kernel.org/r/20161221192112.333161745@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Thomas Gleixner [Wed, 21 Dec 2016 19:19:56 +0000 (20:19 +0100)]
irqchip/gic: Consolidate hotplug state space
Even if both drivers are compiled in only one instance can run on a given
system depending on the available GIC version.
So having seperate hotplug states for them is pointless.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Sebastian Siewior <bigeasy@linutronix.de> Link: http://lkml.kernel.org/r/20161221192112.252416267@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Thomas Gleixner [Wed, 21 Dec 2016 19:19:54 +0000 (20:19 +0100)]
cpu/hotplug: Cleanup state names
When the state names got added a script was used to add the extra argument
to the calls. The script basically converted the state constant to a
string, but the cleanup to convert these strings into meaningful ones did
not happen.
Replace all the useless strings with 'subsys/xxx/yyy:state' strings which
are used in all the other places already.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sebastian Siewior <bigeasy@linutronix.de> Link: http://lkml.kernel.org/r/20161221192112.085444152@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Remove also the now pointless cpu notifier error injection mechanism. The
states can be executed step by step and error rollback is the same as cpu
down, so any state transition can be tested w/o requiring the notifier
error injection.
Some CPU hotplug states are kept as they are (ab)used for hotplug state
tracking.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: rt@linutronix.de Link: http://lkml.kernel.org/r/20161221192112.005642358@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>