Christian König [Fri, 13 Sep 2019 22:38:07 +0000 (17:38 -0500)]
drm/amdgpu: use moving fence instead of exclusive for VM updates
Make VM updates depend on the moving fence instead of the exclusive one.
Makes it less likely to actually have a dependency.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 21 Aug 2019 09:19:52 +0000 (17:19 +0800)]
drm/amd/powerplay: update cached feature enablement status V3
Need to update in cache feature enablement status after pp_feature
settings. Another fix for the commit below:
drm/amd/powerplay: implment sysfs feature status function in smu
V2: update smu_feature_update_enable_state() and relates
V3: use bitmap_or and bitmap_andnot
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 30 Aug 2019 09:30:46 +0000 (17:30 +0800)]
drm/amd/powerplay: guard manual mode prerequisite for clock level force
Force clock level is for dpm manual mode only.
Reported-by: Candice Li <candice.li@amd.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This workaround is better handled in user mode in a way that doesn't
require allocating extra memory and breaking userptr BOs.
The TLB bug is a performance bug, not a functional or security bug.
Hence it is safe to remove this kernel part of the workaround to
allow a better workaround using only virtual address alignments in
user mode.
v2: Removed VI_BO_SIZE_ALIGN definition
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Mon, 26 Aug 2019 22:46:28 +0000 (18:46 -0400)]
drm/amdgpu: Use optimal mtypes and PTE bits for Arcturus
For compute VRAM allocations on Arturus use the new RW mtype
for non-coherent local memory, CC mtype for coherent local
memory and PTE_SNOOPED bit for invalidating non-dirty cache
lines on remote XGMI mappings.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Tested-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Mon, 26 Aug 2019 22:39:11 +0000 (18:39 -0400)]
drm/amdgpu: Determing PTE flags separately for each mapping (v3)
The same BO can be mapped with different PTE flags by different GPUs.
Therefore determine the PTE flags separately for each mapping instead
of storing them in the KFD buffer object.
Add a helper function to determine the PTE flags to be extended with
ASIC and memory-type-specific logic in subsequent commits.
v2: Split Arcturus-specific MTYPE changes into separate commit
v3: Fix return type of get_pte_flags to uint64_t
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Fri, 26 Jul 2019 21:03:11 +0000 (16:03 -0500)]
drm/amdgpu: Support new arcturus mtype
Arcturus repurposed mtype WC to RW. Modify gmc functions
to support the new mtype
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Fri, 26 Jul 2019 20:57:50 +0000 (15:57 -0500)]
drm/amdgpu: Extends amdgpu vm definitions (v2)
Add RW mtype introduced for arcturus.
v2:
* Don't add probe-invalidation bit from UAPI
* Don't add unused AMDGPU_MTYPE_ definitions
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 30 Aug 2019 05:29:18 +0000 (13:29 +0800)]
drm/amdgpu: add helper function to do common ras_late_init/fini (v3)
In late_init for ras, the helper function will be used to
1). disable ras feature if the IP block is masked as disabled
2). send enable feature command if the ip block was masked as enabled
3). create debugfs/sysfs node per IP block
4). register interrupt handler
v2: check ih_info.cb to decide add interrupt handler or not
v3: add ras_late_fini for cleanup all the ras fs node and remove
interrupt handler
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 5 Jun 2019 06:40:57 +0000 (14:40 +0800)]
drm/amdgpu: poll ras_controller_irq and err_event_athub_irq status
For the hardware that can not enable BIF ring for IH cookies for both
ras_controller_irq and err_event_athub_irq, the driver has to poll the
status register in irq handling and ack the hardware properly when there
is interrupt triggered
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 30 May 2019 03:57:20 +0000 (11:57 +0800)]
drm/amdgpu/nbio: add functions to query ras specific interrupt status
ras_controller_interrupt and err_event_interrupt are ras specific interrupts.
add functions to check their status and ack them if they are generated. both
funcitons should only be invoked in ISR when BIF ring is disabled or even not
initialized.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Fri, 6 Sep 2019 06:40:28 +0000 (16:40 +1000)]
Merge tag 'drm-next-5.4-2019-08-30' of git://people.freedesktop.org/~agd5f/linux into drm-next
drm-next-5.4-2019-08-30:
amdgpu:
- Add DC support for Renoir
- Add some GPUVM hw bug workarounds
- add support for the smu11 i2c controller
- GPU reset vram lost bug fixes
- Navi1x powergating fixes
- Navi12 power fixes
- Renoir power fixes
- Misc bug fixes and cleanups
Petr Cvek [Fri, 30 Aug 2019 14:31:58 +0000 (16:31 +0200)]
drm/amdgpu: Fix undefined dm_ip_block for navi12
There is missing "if defined" CONFIG_DRM_AMD_DC block for non DC
configurations. This will cause link error. The patch is fixing that.
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=110979 Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Fri, 14 Dec 2018 03:21:41 +0000 (11:21 +0800)]
drm/amdgpu: fix no interrupt issue for renoir emu (v2)
In renoir's vega10_ih model, there's a security change in mmIH_CHICKEN
register, that limits IH to use physical address (FBPA, GPA) directly.
Those chicken bits need to be programmed first.
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Fri, 30 Aug 2019 01:53:27 +0000 (09:53 +0800)]
drm/amd/powerplay: SMU_MSG_OverridePcieParameters is unsupport for APU
For apu, SMU_MSG_OverridePcieParameters is unsupport.
So return directly in smu_override_pcie_parameters function.
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Handle job is NULL use case in amdgpu_device_gpu_recover
This should be checked at all places job is accessed.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Prike Liang [Thu, 15 Aug 2019 08:53:08 +0000 (16:53 +0800)]
drm/amd/powerplay: add the interface for getting ultimate frequency v3
add the get_dpm_ultimate_freq for supporting different swSMU.
-v2:
Handle the unsupported clock type and read smc message failed case and return error code.
Move the smu12 uclk frequency retrieved logic to renoir ppt.
-v3:
Use goto clause to handle invalidate clk index.
Add the limited tag for smu_get_dpm_uclk to avoid other likewise interface introduced.
Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Prike Liang [Thu, 15 Aug 2019 01:39:06 +0000 (09:39 +0800)]
drm/amd/powerplay: regards the APU always enable the dpm feature mask
There is no driver message to enable/disable feature mask for APU.
For the sake of APU reusing swSMU interface and assume APU supports all
the feature.
Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tianci.Yin [Wed, 28 Aug 2019 02:03:40 +0000 (10:03 +0800)]
drm/amdgpu/psp: keep TMR in visible vram region for SRIOV
Fix compute ring test failure in sriov scenario.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tianci.Yin [Wed, 28 Aug 2019 10:51:19 +0000 (18:51 +0800)]
drm/amdgpu: keep the stolen memory in visible vram region
stolen memory should be fixed in visible region.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 28 Aug 2019 13:47:34 +0000 (08:47 -0500)]
drm/amdgpu/virtual_dce: drop error message in hw_init
No need to add new asic cases. This is a sw display
implementation, so just drop the error message so when
we add new asics, all we have to do is add the virtual
dce IP module.
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jean Delvare [Wed, 28 Aug 2019 15:05:57 +0000 (17:05 +0200)]
drm/amdgpu/si: fix ASIC tests
Comparing adev->family with CHIP constants is not correct.
adev->family can only be compared with AMDGPU_FAMILY constants and
adev->asic_type is the struct member to compare with CHIP constants.
They are separate identification spaces.
Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10") Cc: Ken Wang <Qingqing.Wang@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 27 Aug 2019 08:32:55 +0000 (16:32 +0800)]
drm/amdgpu: introduce vram lost for reset (v2)
for SOC15/vega10 the BACO reset & mode1 would introduce vram lost
in high end address range, current kmd's vram lost checking cannot
catch it since it only check very ahead visible frame buffer
v2:
cover NV as well
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Tue, 27 Aug 2019 14:59:45 +0000 (22:59 +0800)]
drm/amdgpu: fix GFXOFF on Picasso and Raven2
For picasso(adev->pdev->device == 0x15d8)&raven2(adev->rev_id >= 0x8),
firmware is sufficient to support gfxoff.
In commit 98f58ada2d37e, for picasso&raven2,
return directly and cause gfxoff disabled.
Fixes: 98f58ada2d37 ("drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possible") Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Masahiro Yamada [Tue, 27 Aug 2019 06:44:25 +0000 (15:44 +0900)]
drm/amd: remove meaningless descending into amd/amdkfd/
Since commit 04d5e2765802 ("drm/amdgpu: Merge amdkfd into amdgpu"),
drivers/gpu/drm/amd/amdkfd/Makefile does not contain any syntax that
is understood by the build system.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Tue, 27 Aug 2019 07:09:25 +0000 (15:09 +0800)]
drm/amd/display: remove unused function setFieldWithMask
After commit a9f54ce3c603 ("drm/amd/display: Refactoring VTEM"),
there is no caller in tree.
Reported-by: Hulk Robot <hulkci@huawei.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 19 Aug 2019 05:17:53 +0000 (13:17 +0800)]
drm/amd/powerplay: correct Vega20 dpm level related settings
Correct the settings for auto mode and skip the unnecessary
settings for dcefclk and fclk.
Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Implement HW I2C enigne controller to be used by the RAS EEPROM
table manager. This is based on code from ATITOOLs.
v2:
Rename the file and all function prefixes to smu_v11_0_i2c
By Luben's observation always fill the TX fifo to full so
we don't have garbadge interpreted by the slave as valid data.
v3:
Remove preemption disable as the HW I2C controller will not
stop the clock on empty TX fifo and so it's not critical to
keep not empty queue.
Switch to fast mode 400 khz SCL clock for faster read and write.
v5:
Restore clock gating before releasing I2C bus and fix some
style comments.
drm/amd/powerplay: Add interface to lock SMU HW I2C.
v2:
PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict
over I2C bus and engine disable thermal control access to
force SMU stop using the I2C bus until the issue is reslolved.
Expose and call vega20_is_smc_ram_running to skip locking when SMU
FW is not yet loaded.
v3:
Remove the prevoius hack as the SMU found the bug.
v5: Typo fix
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Mon, 26 Aug 2019 08:57:07 +0000 (16:57 +0800)]
drm/amdgpu/display: fix build error without CONFIG_DRM_AMD_DC_DSC_SUPPORT
If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28:
error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control?
dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
^~~~~~~~~~~~~~~~~~~~
dcn20_dpp_pg_control
Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this.
Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Mon, 26 Aug 2019 13:20:12 +0000 (16:20 +0300)]
drm/amd/powerplay: Fix an off by one in navi10_get_smu_msg_index()
The navi10_message_map[] array has SMU_MSG_MAX_COUNT elements so the ">"
has to be changed to ">=" to prevent reading one element beyond the end
of the array.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Since reservation_object_wait_timeout_rcu is called with
interruptable set to false it's wrong to say
'or interrupted' in the error message.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Fri, 16 Aug 2019 08:13:28 +0000 (16:13 +0800)]
drm/amdgpu: add dummy read for some GCVM status registers
The GRBM register interface is now capable of bursting 1 cycle per
register wr->wr, wr->rd much faster than previous muticycle per
transaction done interface. This has caused a problem where status
registers requiring HW to update have a 1 cycle delay, due to the
register update having to go through GRBM.
SW may operate on an incorrect value if they write a register and
immediately check the corresponding status register.
Registers requiring HW to clear or set fields may be delayed by 1 cycle.
For example,
1. write VM_INVALIDATE_ENG0_REQ mask = 5a
2. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a
a. HW will reset VM_INVALIDATE_ENG0_ACK = 0 until invalidation is complete
3. write VM_INVALIDATE_ENG0_REQ mask = 5a
4. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a
a. First read of VM_INVALIDATE_ENG0_ACK = 5a instead of 0
b. Second read of VM_INVALIDATE_ENG0_ACK = 0 because
the remote GRBM h/w register takes one extra cycle to be cleared
c. In this case, SW will see a false ACK if they exit on first read
Dave Airlie [Tue, 27 Aug 2019 07:22:15 +0000 (17:22 +1000)]
Merge tag 'drm-next-5.4-2019-08-23' of git://people.freedesktop.org/~agd5f/linux into drm-next
drm-next-5.4-2019-08-23:
amdgpu:
- Enable power features on Navi12
- Enable power features on Arcturus
- RAS updates
- Initial Renoir APU support
- Enable power featyres on Renoir
- DC gamma fixes
- DCN2 fixes
- GPU reset support for Picasso
- Misc cleanups and fixes
Dave Airlie [Tue, 27 Aug 2019 07:10:30 +0000 (17:10 +1000)]
Merge tag 'drm-misc-next-2019-08-23' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for 5.4:
UAPI Changes:
Cross-subsystem Changes:
Core Changes:
- dma-buf: dma-fence selftests
Driver Changes:
- kirin: Various cleanups and reworks
- komeda: Add support for DT memory-regions
- meson: Rely on the compatible to detect vpu features
- omap: Implement alpha and pixel blend mode properties
- panfrost: Implement per-fd address spaces, various fixes
- rockchip: DSI DT binding rework
- fbdev: Various cleanups
Dave Airlie [Tue, 27 Aug 2019 06:52:06 +0000 (16:52 +1000)]
Merge tag 'imx-drm-next-2019-08-23' of git://git.pengutronix.de/pza/linux into drm-next
drm/imx: IPUv3 image converter fixes and improvements
Fix image converter seam handling for 1024x1024 pixel hardware
limitation at the main processing section input, improve error
handling, and slightly optimize for 1:1 conversions.
Add support for newly defined 32-bit RGB V4L2 pixel formats.
Dave Airlie [Tue, 27 Aug 2019 06:36:41 +0000 (16:36 +1000)]
Merge tag 'drm-intel-next-2019-08-22' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- More TGL enabling work (Michel, Jose, Lucas)
- Fixes on DP MST (Ville)
- More GTT and Execlists fixes and improvements (Chris)
- Code style clean-up on hdmi and dp side (Jani)
- Fix null pointer dereferrence (Xiong)
- Fix a couple of missing serialization on selftests (Chris)
- More vm locking rework (Chris)
drm-intel-next-2019-08-20:
- GuC and HuC related fixes and improvements (Daniele, Michal)
- Improve debug with more engine information and rework on debugfs files (Chris, Stuart)
- Simplify appearture address handling (Chris)
- Other fixes and cleanups around engines and execlists (Chris)
- Selftests fixes (Matt, Chris)
- Gen11 cache flush related fixes and improvements (Mika)
- More work around requests, timelines and locks to allow removal of struct_mutex (Chris)
- Add missing CML PCI ID (Anusha)
- More work on the new i915 buddy allocator (Matt)
- More headers, files and directories reorg (Daniele)
- Improvements on ggtt’s get pdp (Mika)
- Fix GPU reset (Chris)
- Fix GPIO pins on gen11 (Matt)
- Fix HW readout for crtc_clock in HDMI mode (Imre)
- Sanitize display Phy during unitit to workaround messages of HW state change during suspend (Imre)
- Be defensive when starting vma activity (Chris)
- More Tiger Lake enabling work (Michel, Daniele, Lucas)
- Relax pd_used assertion (Chris)
drm-intel-next-2019-08-13:
- More Tiger Lake enabling work (Lucas, Jose, Tomasz, Michel, Jordan, Anusha, Vandita)
- More selftest organization reworks, fixes and improvements (Lucas, Chris)
- Simplifications on GEM code like context and cleanup_early (Chris, Daniele)
- GuC and HuC related fixes and improvements (Daniele, Michal, Chris)
- Some clean up and fixes on headers, Makefile, and generated files (Lucas, Jani)
- MOCS setup clean up (Tvrtko)
- More Elkhartlake enabling work (Jose, Matt)
- Fix engine reset by clearing in flight execlists requests (Chris)
- Fix possible memory leak on intel_hdcp_auth_downstream (Wei)
- Introduce intel_gt_runtime_suspend/resume (Daniele)
- PMU improvements (Tvrtko)
- Flush extra hard after writing relocations through the GTT (Chris)
- Documentations fixes (Michal, Chris)
- Report dma_reserv allocation failure (Chris)
- Improvements around shrinker (Chris)
- More improvements around engine handling (Chris)
- Also more s/dev_priv/i915 (Chris)
- Abstract display suspend/resume operations (Rodrigo/Jani)
- Drop VM_IO from GTT mappings (Chris)
- Fix some NULL vs IS_ERR conditions (Dan)
- General improvements on error state (Chris)
- Isolate i915_getparam_iocrtl to its own file (Chris)
- Perf OA object refactor (Umesh)
- Ignore central i915->kernel_context and allocate it directly (Chris)
- More fixes and improvements around wakerefs (Chris)
- Clean-up and improvements around debugfs (Chris)
- Free the imported shmemfs file for phys objects (Chris)
- Many other fix and cleanups around engines and execlists (Chris)
- Split out uncore_mmio_debug (Daniele)
- Memory management fixes for blk and gtt (Matt)
- Introduction of buddy allocator to handle huge-pages for GTT (Matt)
- Fix ICL and TGL PG3 power domains (Anshuman)
- Extract GT IRQ to gt/ (Andi)
- Drop last_fence tracking in favor of whole vma->active (Chris)
- Make overlay to use i915_active instead of i915_active_request (Chris)
- Move misc display IRQ handling to its own function (Jose)
- Introduce new _TRANS2() macro in preparation for some coming PSR related work (Jose)
Matthew Ruffell [Thu, 15 Aug 2019 04:26:40 +0000 (16:26 +1200)]
drm/hisilicon/hibmc: Make CONFIG_DRM_HISI_HIBMC depend on ARM64
Hisilicon developed hibmc_drm for their arm64 based soc and did not
intend for this driver to be used on any other architecture than arm64.
Using it on amd64 leads to incorrect video modes being used, making
the screen unreadable, forcing users to manually blacklist the module
on the kernel command line to use the d-i server installer or any
graphical sessions.
Make CONFIG_DRM_HISI_HIBMC firmly depend on ARM64 to ensure it is not
built for other architectures.
Signed-off-by: Matthew Ruffell <matthew.ruffell@canonical.com> Signed-off-by: Xinliang Liu <z.liuxinliang@hisilicon.com>
hersen wu [Fri, 2 Aug 2019 20:01:37 +0000 (16:01 -0400)]
drm/amd/display: flicking observed while installing driver on Navi10 CF
[WHY] value of dchub_ref_clock is decided by dchubbub global timer
settings which is programmed by vbios command table disp_init.
for multi-GPU case, vbios is posted only for primary GPU. without
vbios posted for the secondary GPU, value of dchub_ref_clock is not
set properly. this value will affect dcn bandwidth calcuation and
cause underflow. user will see screen flicking during driver
installation for dual GPU case.
[HOW] dc init_hw always call vbios command table disp_init to
make sure dchubbub global timer is configured and enable.
Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>