Linus Walleij [Tue, 20 Jun 2017 08:07:34 +0000 (10:07 +0200)]
Merge tag 'samsung-pinctrl-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers update for v4.13:
1. Split drivers per ARMv7 and ARMv8 architectures because there
is no need to compile everything on each of them.
2. Fix for possible NULL-pointer dereference after memory allocation
failure.
3. Cleanups (silencing cast warnings, constify, removal of unneeded
casts, removal of modular boiler-plate).
Hanna Hawa [Mon, 12 Jun 2017 15:34:57 +0000 (17:34 +0200)]
pinctrl: mvebu: add driver for Armada CP110 pinctrl
This commit adds a pinctrl driver for the CP110 part of the Marvell
Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
the MPP pins are available. On the other side, the Armada 8K has two
CP110, and the available MPPs are split between the master CP110 (MPPs 32
to 62) and the slave CP110 (MPPs 0 to 31).
The register interface to control the MPPs is however the same as all
other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic.
Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Shadi Ammouri <shadi@marvell.com>
[updated for mvebu pinctrl and 4.9 changes:
- converted to simple_mmio
- converted to syscon/regmap
- removed unimplemented .remove function
- dropped DTS changes
- defered gpio ranges to DT
- fixed warning
- properly set soc->nmodes
-- rmk] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
[ add missing MPP[61:56] function 14 (SDIO)
-- Konstantin Porotchkin] Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[ allow to properly register more then one instance of this driver
-- Grzegorz Jaszczyk] Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[ - rebased on 4.12-rc1
- fixed the 80 character limit for mvebu_mpp_mode array
- aligned the compatible name on the ones already used
- fixed the MPP table for CP110: some MPP are not available on Armada 7K
-- Gregory CLEMENT] Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Hanna Hawa [Mon, 12 Jun 2017 15:34:56 +0000 (17:34 +0200)]
pinctrl: mvebu: add driver for Armada AP806 pinctrl
This commit adds a pinctrl driver for the pin-muxing controller found in
the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register
interface is compatible with the one used by previous mvebu pin
controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c
is used.
Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Shadi Ammouri <shadi@marvell.com>
[updated for mvebu pinctrl changes
- converted to simple_mmio
- removed unimplemented .remove function
- removed DTS description
- converted to use syscon/regmap
--rmk] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gregory CLEMENT [Mon, 12 Jun 2017 15:34:53 +0000 (17:34 +0200)]
pinctrl: mvebu: remove the offset property for regmap
The offset property of the pinctrl node, when a regmap is used in the
device tree, was never used nor documented in the binding. Moreover, the
compatible string is enough to let the driver know which offset using.
So this patch removes the property and move the information at the driver
level.
Jerome Brunet [Thu, 8 Jun 2017 13:09:48 +0000 (15:09 +0200)]
pinctrl: meson-gxl: add tsin_a pins
Add Tsin A pins to bank DV and X.
We don't have a driver for the tsin yet but since the tsin A pinmux is
enabled by default at boot time, declaring this pinmux is required to
properly operate on GPIOX.
Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output
as the tsin A seems to have priority.
Mika Westerberg [Tue, 6 Jun 2017 13:18:18 +0000 (16:18 +0300)]
pinctrl: intel: Make it possible to specify mode per pin in a group
On some SoCs not all pins in a group use the same mode when a certain
function is muxed out of them. This makes it possible to specify mode per
pin as an array instead in addition to single integer.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mika Westerberg [Tue, 6 Jun 2017 13:18:17 +0000 (16:18 +0300)]
pinctrl: intel: Add support for variable size pad groups
The Intel GPIO hardware has a concept of pad groups, which means 1 to 32
pads occupying their own GPI_IS, GPI_IE, PAD_OWN and so on registers. The
existing hardware has the same amount of pads in each pad group (except the
last one) so it is possible to use community->gpp_size to calculate start
offset of each register.
With the next generation SoCs the pad group size is not always the same
anymore which means we cannot use community->gpp_size for register offset
calculations directly.
To support variable size pad groups we introduce struct intel_padgroup that
can be filled in by the client drivers according the hardware pad group
layout. The core driver will always use these when it performs calculations
for pad register offsets. The core driver will automatically populate pad
groups based on community->gpp_size if the driver does not provide any.
This makes sure the existing drivers still work as expected.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Chuah, Kim Tatt <kim.tatt.chuah@intel.com> Signed-off-by: Tan Jui Nee <jui.nee.tan@intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Alexandre TORGUE [Wed, 31 May 2017 09:10:43 +0000 (11:10 +0200)]
pinctrl: stm32: remove useless check
There is no link between the number of elements of tab which contains all
pin desc (located in each pinctrl-stm32xxxx.c files) and the pin number
(defined in the tab).
The iomem pointer is used safely (stored under priv by
s5pv210_retention_init(), used by s5pv210_retention_disable()) thus we
can add explicit casts to iomem to silence the warning.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
pinctrl: samsung: Handle memory allocation failure during wakeup banks init
Check if kmemdup failed during wakeup banks initialization. Otherwise
NULL pointer would be stored under "irq_chip" member of bank and later
dereferenced in interrupt handler.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
pinctrl: samsung: Constify wakeup driver specific data
Static exynos_irq_chip structures, containing driver specific data, are
referenced only through opaque data pointer in const of_device_id table.
The contents of pointed memory (exynos_irq_chip structure itself) is
then copied with kmemdup() during wakeup initialization so
exynos_irq_chip can be made const for code safenes.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
pinctrl: samsung: Split Exynos drivers per ARMv7 and ARMv8
Exynos pinctrl drivers contain pretty big per-SoC data structures. The
pinctrl-exynos object file contained code and data for both ARMv7 and
ARMv8 SoCs thus it grew big. There will not be a shared image between
ARMv7 and ARMv8 so there is no need to combine all of this into one
driver.
Splitting the data allows to make it more granular (e.g. code related to
ARMv8 Exynos is self-contained), slightly speed up the compilation and
reduce the effective size of compiled kernel.
The common data structures and functions reside still in existing
pinctrl-exynos.c. Only the SoC-specific parts were moved out to new
files. Except marking few functions non-static and adding them to
header, there were no functional changes in the code.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Arnd Bergmann [Tue, 30 May 2017 09:11:28 +0000 (11:11 +0200)]
pinctrl: mcp23s08: improve I2C Kconfig dependency
With "SPI_MASTER=y && I2C=m", we can build mcp23s08 as a built-in driver,
which then results in a link failure:
drivers/pinctrl/built-in.o: In function `mcp23s08_probe_one.isra.0':
:(.text+0x7910): undefined reference to `__devm_regmap_init_i2c'
drivers/pinctrl/built-in.o: In function `mcp23s08_init':
:(.init.text+0x110): undefined reference to `i2c_register_driver'
drivers/pinctrl/built-in.o: In function `mcp23s08_exit':
:(.exit.text+0x3c): undefined reference to `i2c_del_driver'
To avoid the problem, this adds another dependency on I2C that enforces
mcp23s08 to be a loadable module whenever the I2C core is a module.
Fixes: 64ac43e6fa28 ("gpio: mcp23s08: move to pinctrl") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
David Wu [Fri, 26 May 2017 07:20:20 +0000 (15:20 +0800)]
pinctrl: rockchip: Add iomux-route switching support
On the some rockchip SOCS, some things like rk3399 specific uart2 can use
multiple pins. Somewhere between the pin io-cells and the uart it seems
to have some sort of switch to decide to which pin to actually route the
data.
+-------+ +--------+ /- GPIO4_B0 (pinmux 2)
| uart2 | -- | switch | --- GPIO4_C0 (pinmux 2)
+-------+ +--------+ \- GPIO4_C3 (pinmux 2)
(switch selects one of the 3 pins base on the GRF_SOC_CON7[BIT0, BIT1])
The routing switch is determined by one pin of a specific group to be set
to its special pinmux function. If the pinmux setting is wrong for that
pin the ip block won't work correctly anyway.
Paul Gortmaker [Mon, 22 May 2017 20:56:48 +0000 (16:56 -0400)]
pinctrl: bcm: clean up modular vs. non-modular distinctions
Fixups here tend to be more of a conglomerate of some of the other
repeated/systematic ones we've seen in the earlier pinctrl cleanups.
We remove module.h from code that isn't doing anything modular at
all; if they have __init sections, then replace it with init.h
One driver has a .remove that would be dispatched on module_exit,
and as that code is essentially orphaned, so we remove it. In case
anyone was previously doing the (pointless) unbind to get to that
function, we disable unbind for this one driver as well.
A couple bool drivers (hence non-modular) are converted over to
to builtin_platform_driver().
Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.
Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
We also delete the MODULE_LICENSE tag etc. since all that information
was (or is now) contained at the top of the file in the comments.
Cc: Eric Anholt <eric@anholt.net> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Jon Mason <jonmason@broadcom.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Sherman Yin <syin@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: linux-gpio@vger.kernel.org Cc: linux-rpi-kernel@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Gortmaker [Mon, 22 May 2017 20:56:47 +0000 (16:56 -0400)]
pinctrl: tegra: clean up modular vs. non-modular distinctions
None of the Kconfigs for any of these drivers are tristate,
meaning that they currently are not being built as a module by anyone.
Lets remove the modular code that is essentially orphaned, so that
when reading the drivers there is no doubt they are builtin-only. All
drivers get similar changes, so they are handled in batch.
We remove module.h from code that isn't doing anything modular at
all; if they have __init sections, then replace it with init.h.
A couple drivers have module_exit() code that is essentially orphaned,
and so we remove that.
Quite a few bool drivers (hence non-modular) are converted over to
to builtin_platform_driver().
Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.
Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
We also delete the MODULE_LICENSE tag etc. since all that information
was (or is now) contained at the top of the file in the comments.
pinctrl: samsung: Add include guard to local header
The pinctrl-exynos.h header is included only once so till now it did not
require an include guard. However adding such is harmless and makes
code prepared for more inclusions.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Gregory CLEMENT [Fri, 19 May 2017 16:04:43 +0000 (18:04 +0200)]
MAINTAINERS: extend mvebu SoC entry with pinctrl drivers
There was no entry for the mvebu pinctrl drivers. As they are tightly
linked to the SoCs and there is a lot of common code to support the
various pinctrl of each SoCs, then add a new entry for the mvebu
maintainers.
This moves irq property handling from spi/i2c specific code into
the generic mcp23s08_probe_one. This is possible because the
device properties are named equally.
As a side-effect this drops support for setting the properties via
pdata, which has no mainline users. If boardcode wants to enable
the chip as interrupt controller it can attach the device properties
instead.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Instead of using custom caching, this switches to regmap based
caching. Before the conversion the debugfs file used uncached
values, so that it was easily possible to see power-loss related
problems. The new code will check and recover at this place.
The patch will also ensure, that irqs are not cleared by checking
register status in debugfs.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
mcp23s08 support configuration of the pullups using the
pinconf framework. This removes the custom pullup configuration
from platform data, which has no upstream users.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:53:07 +0000 (18:53 +0200)]
MIPS: jz4740: Remove custom GPIO code
All the drivers for the various hardware elements of the jz4740 SoC have
been modified to use the pinctrl framework for their pin configuration
needs.
As such, this platform code is now unused and can be deleted.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:52:58 +0000 (18:52 +0200)]
MIPS: ingenic: Enable pinctrl for all ingenic SoCs
There is a pinctrl driver for each of the Ingenic SoCs supported by the
upstream Linux kernel. In order to switch away from the old GPIO
platform code, we now enable the pinctrl drivers by default for the
Ingenic SoCs.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:53:06 +0000 (18:53 +0200)]
pwm: jz4740: Let the pinctrl driver configure the pins
Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.
One inherent problem of this new approach is that the pinctrl framework
does not allow us to configure each pin on demand, when the various PWM
channels are requested or released. For instance, the PWM channels can
be configured from sysfs, which would require all PWM pins to be configured
properly beforehand for the PWM function, eventually causing conflicts
with other platform or board drivers.
The proper solution here would be to modify the pwm-jz4740 driver to
handle only one PWM channel, and create an instance of this driver
for each one of the 8 PWM channels. Then, it could use the pinctrl
framework to dynamically configure the PWM pin it controls.
Until this can be done, the only jz4740 board supported upstream
(Qi lb60) can configure all of its connected PWM pins in PWM function
mode, since those are not used by other drivers nor by GPIOs on the
board.
Paul Cercueil [Fri, 12 May 2017 16:52:55 +0000 (18:52 +0200)]
dt/bindings: Document gpio-ingenic
This commit adds documentation for the devicetree bindings of the
gpio-ingenic driver, which handles GPIOs of the Ingenic SoCs
currently supported by the Linux kernel.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Paul Cercueil [Fri, 12 May 2017 16:52:54 +0000 (18:52 +0200)]
dt/bindings: Document pinctrl-ingenic
This commit adds documentation for the devicetree bindings of the
pinctrl-ingenic driver, which handles pin configuration and pin
muxing of the Ingenic SoCs currently supported by the Linux kernel.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: When claiming hog, skip maps not served by same device
When pinctrl device registers, it automatically claims hogs, that is,
maps that pinctrl device serves for itself.
It is possible that in addition to SoC's pinctrl device, other pinctrl
devices get registered. E.g. some gpio expander devies are registered
as pinctrl devices. For such devices, pinctrl maps could be defined
that set up SoC's pins (e.g. interrupt pin for gpio expander). Such
a map will have target device set to gpio expander.
Here is device tree snippet that causes this scenario:
Such a map will have target device set to gpio expander. However is not
a hog, it is a regular map that is claimed by core before gpio expander
device is probed.
Thus when looking for hogs, it is not enough to check that map's target
device is set to pinctrl device being registered. Need also check that
map's control device is also set to the same.
Dong Aisheng [Fri, 19 May 2017 07:05:43 +0000 (15:05 +0800)]
pinctrl: imx: add soc specific mux_mode mask and shift property
MX7ULP MUX mode mask and shift bit is different from VF610.
Let's make it a platform specific property for the later easy of
adding MX7ULP support.
One trick in exist code that Vybrid hardcoded the config part
as 0xffff because its mux_config register BIT[15-0] are all configs
part. But it's not true in ULP, so use mux_mask instead to address
the difference.
Dong Aisheng [Fri, 19 May 2017 07:05:42 +0000 (15:05 +0800)]
pinctrl: imx: add generic pin config core support
The design is based on the exist architecture that the core will
provide a uniformed way to decode the generic pin config into platform
config register raw data according to the imx_cfg_params_decode maps
registered by platform.
Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT,
are created for platform to register decode map conveniently.
In order to cope with some special case, a platform specific fixup()
function is also available to use.
Note that rather than fully utilizing the generic pinconf support
provided by pinctrl core, IMX only adopts the device tree bindings
of generic pinconf. The config used in .pin_config_get[set] are raw
register data instead of generic one which makes us align the exist
using. And that's also why we cannot set pinconf_ops.is_generic.
If 'devm_kzalloc' fails, a NULL pointer will be dereferenced.
Return -ENOMEM instead, as done for the other memory allocation just a
few lines below.
BTW, change the 'devm_kzalloc' into a 'devm_kcalloc'.
Sean Wang [Mon, 1 May 2017 07:54:34 +0000 (15:54 +0800)]
pinctrl: mediatek: reuse pinctrl driver for mt7623
mt7623 pinctrl hardware can be compatible with mt2701 driver,
so the patch lets the pinctrl on mt7623 SoC reuse the driver
and deletes those redundant ones.
Signed-off-by: Sean Wang <sean.wang@mediatek.com> Acked-by: John Crispin <john@phrozen.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the missing pins for the PWM controllers found in Amlogic
Meson8 SoCs. This includes the pins for PWM_A, PWM_B, PWM_C, PWM_D,
PWM_E and PWM_F controllers.
There is an additional PWM function with the name PWM_VS in the vendor
kernel sources which seems to be used for external video input. Thus
it's not part of this change as the IP block behind the pwm-meson driver
is not responsible for these pins.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl/amd: Update contact information for AMD pinctrl/amd
Updating the point of contact for AMD GPIO driver.
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Signed-off-by: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> Cc: Ken Xue <Ken.Xue@amd.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
projects / linux.git / log