Dave Airlie [Wed, 21 Mar 2018 04:07:03 +0000 (14:07 +1000)]
Merge tag 'omapdrm-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next
omapdrm patches for v4.17
* Fix sparse warnings from omapdrm
* HPD support for DVI connector
* Big cleanup to remove static variables
* tag 'omapdrm-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux: (69 commits)
drm/omap: fix compile error when DPI is disabled
drm/omap: fix compile error when debugfs is disabled
drm: omapdrm: displays: panel-dsi-cm: Fix field access before set
drm/omap: cleanup color space conversion
drm/omap: Allow HDMI audio setup even if we do not have video configured
drm/omap: fix maximum sizes
drm/omap: add writeback funcs to dispc_ops
drm/omap: fix scaling limits for WB
drm/omap: fix WB height with interlace
drm/omap: fix WBDELAYCOUNT with interlace
drm/omap: fix WBDELAYCOUNT for HDMI
drm/omap: set WB channel-in in wb_setup()
drm/omap: Add pclk setting case when channel is DSS_WB
drm/omap: dispc: disp_wb_setup to check return code
drm/omap: remove leftover enums
dt-bindings: display: add HPD gpio to DVI connector
drm/omap: add HPD support to connector-dvi
drm/omap: Init fbdev emulation only when we have displays
drm/omap: cleanup fbdev init/free
drm/omap: fix omap_fbdev_free() when omap_fbdev_create() wasn't called
...
Dave Airlie [Wed, 21 Mar 2018 04:06:00 +0000 (14:06 +1000)]
Merge tag 'drm-msm-next-2018-03-20' of git://people.freedesktop.org/~robclark/linux into drm-next
Updates for 4.17. Sorry, running a bit late on this, didn't have a
chance to send pull-req before heading to linaro. But it has all been
in linux-next for a while. Main updates:
+ DSI updates from 10nm / SDM845
+ fix for race condition with a3xx/a4xx fence completion irq
+ some refactoring/prep work for eventual a6xx support (ie. when we have
a userspace)
+ a5xx debugfs enhancements
+ some mdp5 fixes/cleanups to prepare for eventually merging writeback
support (ie. when we have a userspace)
* tag 'drm-msm-next-2018-03-20' of git://people.freedesktop.org/~robclark/linux: (36 commits)
drm/msm: fix building without debugfs
drm/msm/mdp5: don't pre-reserve LM's if no dual-dsi
drm/msm/mdp5: add missing LM flush bits
drm/msm/mdp5: print a bit more of the atomic state
drm/msm/mdp5: rework CTL START signal handling
drm/msm: Trigger fence completion from GPU
drm/msm/dsi: fix direct caller of msm_gem_free_object()
drm/msm: strip out msm_fence_cb
drm/msm: rename mdp->disp
drm/msm/dsi: Fix potential NULL pointer dereference in msm_dsi_modeset_init
drm/msm/adreno/a5xx_debugfs: fix potential NULL pointer dereference
drm/msm/dsi: Get byte_intf_clk only for versions that need it
drm/msm/adreno: Use generic function to load firmware to a buffer object
drm/msm/adreno: Define a list of firmware files to load per target
drm/msm/adreno: Rename gpmufw to powerfw
drm/msm: Pass the correct aperture end to drm_mm_init
drm/msm/gpu: Set number of clocks to 0 if the list allocation fails
drm/msm: Replace gem_object deprecated functions
drm/msm/hdmi: fix semicolon.cocci warnings
drm/msm/mdp5: Fix trailing semicolon
...
Dave Airlie [Wed, 21 Mar 2018 04:04:38 +0000 (14:04 +1000)]
Merge tag 'drm/tegra/for-4.17-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v4.17-rc1
This fixes mmap() for fbdev devices by providing a custom implementation
based on the KMS variant. This is a fairly exotic case these days, hence
why it is not flagged for stable.
There is also support for dedicating one of the overlay planes to serve
as a hardware cursor on older Tegra that did support hardware cursors
but not RGBA formats for it.
Planes will now also export the IN_FORMATS property by supporting the
various block-linear tiling modifiers for RGBA pixel formats.
Other than that, there's a bit of cleanup of DMA API abuse, use of the
private object infrastructure for global state (rather than subclassing
atomic state objects) and an implementation of ->{begin,end}_cpu_access
callbacks for PRIME exported buffers, which allow users to perform cache
maintenance on these buffers.
* tag 'drm/tegra/for-4.17-rc1' of git://anongit.freedesktop.org/tegra/linux:
drm/tegra: prime: Implement ->{begin,end}_cpu_access()
drm/tegra: gem: Map pages via the DMA API
drm/tegra: hub: Use private object for global state
drm/tegra: fb: Properly support linear modifier
drm/tegra: plane: Support format modifiers
drm/tegra: dc: Dedicate overlay plane to cursor on older Tegra's
drm/tegra: plane: Make tegra_plane_get_overlap_index() static
drm/tegra: fb: Implement ->fb_mmap() callback
drm/tegra: gem: Make __tegra_gem_mmap() available more widely
drm/tegra: gem: Reshuffle declarations
Dave Airlie [Wed, 21 Mar 2018 03:58:43 +0000 (13:58 +1000)]
Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into drm-next
I have accumulated some patches as we went through some internal testing
for mali-dp and I was waiting for the YUV2RGB patches to land in your
tree.
* 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld:
drm: mali-dp: Add YUV->RGB conversion support for video layers
drm: mali-dp: Turn off CRTC vblank when removing module.
drm: arm: malidp: Use drm_atomic_helper_shutdown() to disable planes on removal
drm: arm: malidp: Don't destroy planes manually in error handlers
drm/mali-dp: Fix malidp_atomic_commit_hw_done() for event sending.
drm/arm/malidp: Disable pixel alpha blending for colors that do not have alpha
drm: mali-dp: Fix bug on scaling with rotation
drm/mali-dp: Don't enable scaling engine for planes that only rotate.
drm: mali-dp: Uninitialized variable in malidp_se_check_scaling()
drm/mali-dp: Align pitch size to be multiple of bus burst read size.
drm/mali-dp: Rotated planes need a larger pitch size.
Dave Airlie [Wed, 21 Mar 2018 01:46:05 +0000 (11:46 +1000)]
Merge branch 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux into drm-next
- Continued cleanup and restructuring of powerplay
- Fetch VRAM type from vbios rather than hardcoding for SOC15 asics
- Allow ttm to drop its backing store when drivers don't need it
- DC bandwidth calc updates
- Enable DC backlight control pre-DCE11 asics
- Enable DC on all supported asics
- DC Fixes for planes due to the way our hw is ordered vs what drm expects
- DC CTM/regamma fixes
- Misc cleanup and bug fixes
* 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: (89 commits)
amdgpu/dm: Default PRE_VEGA ASIC support to 'y'
drm/amd/pp: Remove the cgs wrapper for notify smu version on APU
drm/amd/display: fix dereferencing possible ERR_PTR()
drm/amd/display: Refine disable VGA
drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel
drm/radeon: Don't turn off DP sink when disconnected
drm/amd/pp: Rename file name cz_* to smu8_*
drm/amd/pp: Replace function/struct name cz_* with smu8_*
drm/amd/pp: Remove unneeded void * casts in cz_hwmgr.c/cz_smumgr.c
drm/amd/pp: Mv cz uvd/vce pg/dpm functions to cz_hwmgr.c
drm/amd/pp: Remove dead header file pp_asicblocks.h
drm/amd/pp: Delete dead code on cz_clockpowergating.c
drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c
drm/amdgpu: Remove wrapper layer of smu ip functions
drm/amdgpu: Don't compared ip_block_type with ip_block_index
drm/amdgpu: Plus NULL function pointer check
drm/amd/pp: Move helper functions to smu_help.c
drm/amd/pp: Replace rv_* with smu10_*
drm/amd/pp: Fix function parameter not correct
drm/amd/pp: Add rv_copy_table_from/to_smc to smu backend function table
...
Arnd Bergmann [Mon, 26 Feb 2018 09:49:26 +0000 (10:49 +0100)]
drm/msm: fix building without debugfs
The adreno driver stopped building when CONFIG_DEBUGFS is disabled:
drivers/gpu/drm/msm/adreno/adreno_device.c: In function 'adreno_load_gpu':
drivers/gpu/drm/msm/adreno/adreno_device.c:153:16: error: 'const struct msm_gpu_funcs' has no member named 'debugfs_init'
if (gpu->funcs->debugfs_init) {
^~
drivers/gpu/drm/msm/adreno/adreno_device.c:154:13: error: 'const struct msm_gpu_funcs' has no member named 'debugfs_init'
gpu->funcs->debugfs_init(gpu, dev->primary);
^~
This adds an #ifdef around the code that references the hidden
pointer.
Fixes: 331dc0bc195b ("drm/msm: add a5xx specific debugfs") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 19 Feb 2018 13:17:06 +0000 (08:17 -0500)]
drm/msm/mdp5: rework CTL START signal handling
For DSI cmd-mode and writeback, we need to write the CTL's START
register to kick things off, but we only want to do that once both
the encoder and the crtc have a chance to write their corresponding
flush bits. The difficulty is that when there is a full modeset
(ie. encoder state has changed) we want to defer the start until
encoder->enable(). But if only plane's have changed, we want to do
this from crtc->commit().
The start_mask was a previous attempt to handle this, but it didn't
really do the right thing since atomic conversion.
Instead track in the crtc state that the start should be deferred,
set to try from encoder's (or in future writeback's) atomic_check().
This way the state is part of the atomic state, and rollback can
work properly if an atomic test fails.
Bjorn Andersson [Wed, 14 Feb 2018 06:46:58 +0000 (22:46 -0800)]
drm/msm: Trigger fence completion from GPU
Interrupt commands causes the CP to trigger an interrupt as the command
is processed, regardless of the GPU being done processing previous
commands. This is seen by the interrupt being delivered before the
fence is written on 8974 and is likely the cause of the additional
CP_WAIT_FOR_IDLE workaround found for a306, which would cause the CP to
wait for the GPU to go idle before triggering the interrupt.
Instead we can set the (undocumented) BIT(31) of the CACHE_FLUSH_TS
which will cause a special CACHE_FLUSH_TS interrupt to be triggered from
the GPU as the write event is processed.
Add CACHE_FLUSH_TS to the IRQ masks of A3xx and A4xx and remove the
workaround for A306.
Suggested-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 14 Feb 2018 16:14:23 +0000 (11:14 -0500)]
drm/msm/dsi: fix direct caller of msm_gem_free_object()
This should be using drm_gem_object_put(). Also since this is done only
in driver unload path, we don't need to synchronize setting tx_gem_obj
to NULL, so juse use the _unlocked() variant.
Rob Clark [Mon, 12 Feb 2018 13:18:27 +0000 (08:18 -0500)]
drm/msm: rename mdp->disp
Since new display controller is called "dpu" instead of "mdp". Lets
make the name of the toplevel directory for the display controllers a
bit more generic.
Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Sean Paul <seanpaul@chromium.org>
drm/msm/dsi: Fix potential NULL pointer dereference in msm_dsi_modeset_init
_dev_ is being dereferenced before it is null checked, hence there
is a potential null pointer dereference.
Fix this by moving the pointer dereference after _dev_ has been
null checked.
Fixes: d4e7f38d70ef ("drm/msm/dsi: check msm_dsi and dsi pointers before use") Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
_minor_ is being dereferenced before it is null checked, hence there
is a potential null pointer dereference. Fix this by moving the pointer
dereference after _minor_ has been null checked.
Fixes: 024ad8df763f ("drm/msm: add a5xx specific debugfs") Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
These callbacks allow the exporter to swap in and pin the backing
storage for buffers as well as invalidate the cache in preparation for
accessing the buffer from the CPU, and flush the cache and unpin the
backing storage when the CPU is done modifying the buffer.
Thierry Reding [Wed, 13 Dec 2017 11:22:48 +0000 (12:22 +0100)]
drm/tegra: gem: Map pages via the DMA API
When allocating pages, map them with the DMA API in order to invalidate
caches. This is the correct usage of the API and works just as well as
faking up the SG table and using the dma_sync_sg_for_device() function.
Harry Wentland [Wed, 8 Nov 2017 20:58:25 +0000 (15:58 -0500)]
amdgpu/dm: Default PRE_VEGA ASIC support to 'y'
Even though we default PRE_VEGA support to 'n' upstream in amd-staging
we want to keep it enabled by default.
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Thu, 15 Mar 2018 10:31:00 +0000 (16:01 +0530)]
drm/amd/display: fix dereferencing possible ERR_PTR()
This patch fixes static checker warning caused by
"36cc549d5986: "drm/amd/display: disable CRTCs with
NULL FB on their primary plane (V2)"
Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Clark Zheng [Thu, 15 Mar 2018 06:02:06 +0000 (14:02 +0800)]
drm/amd/display: Refine disable VGA
bad case won't follow normal sense, it will not enable vga1 as usual, but vga2,3,4 is on.
Signed-off-by: Clark Zheng <clark.zheng@amd.com> Reviewed-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel
and amdgpu_bo_create_reserved.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thierry Reding [Thu, 15 Mar 2018 15:44:04 +0000 (16:44 +0100)]
drm/tegra: plane: Support format modifiers
Pass the list of valid format modifiers to planes upon initialization
and implement the ->format_mod_supported() callback so that userspace
can query for the valid combinations of formats and modifiers.
Rex Zhu [Wed, 14 Mar 2018 12:05:12 +0000 (20:05 +0800)]
drm/amd/pp: Rename file name cz_* to smu8_*
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 14 Mar 2018 09:29:54 +0000 (17:29 +0800)]
drm/amd/pp: Replace function/struct name cz_* with smu8_*
hw ip smu8 was used on CZ/ST,
so use smu8 as the prefix of the function/struct name in powerplay.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 13 Mar 2018 08:50:44 +0000 (16:50 +0800)]
drm/amd/pp: Remove unneeded void * casts in cz_hwmgr.c/cz_smumgr.c
Removes unneeded void * casts for the following pointers:
hwmgr->backend
hwmgr->smu_backend
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 13 Mar 2018 07:44:42 +0000 (15:44 +0800)]
drm/amd/pp: Mv cz uvd/vce pg/dpm functions to cz_hwmgr.c
1. delete cz_clockpowergating.c/.h files
2. mark uvd/vce dpm/pg functions static
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 13 Mar 2018 07:35:17 +0000 (15:35 +0800)]
drm/amd/pp: Remove dead header file pp_asicblocks.h
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 13 Mar 2018 07:27:06 +0000 (15:27 +0800)]
drm/amd/pp: Delete dead code on cz_clockpowergating.c
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 12 Mar 2018 11:52:23 +0000 (19:52 +0800)]
drm/amdgpu: Remove wrapper layer of smu ip functions
1. delete amdgpu_powerplay.c used for wrapping smu ip functions
2. delete struct pp_instance,
3. make struct hwmgr as the smu hw handle.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 14 Mar 2018 07:38:48 +0000 (15:38 +0800)]
drm/amdgpu: Don't compared ip_block_type with ip_block_index
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 12 Mar 2018 11:50:38 +0000 (19:50 +0800)]
drm/amdgpu: Plus NULL function pointer check
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 9 Mar 2018 11:52:26 +0000 (19:52 +0800)]
drm/amd/pp: Move helper functions to smu_help.c
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 7 Mar 2018 05:32:45 +0000 (13:32 +0800)]
drm/amd/pp: Delete is_smc_ram_running function on RV
1. There is a race condition when another ip also use same register pairs
2. check once at boot up by GetDriverIfVersion message is sufficient
to check SMU health. so delete is_smc_ram_running check.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: Fix KASAN user after free on driver unload.
Reusing local handle to initialize BO without resetting it to
NULL is wrong since it causes amdgpu_bo_create_reserved to skip
new BO creation and just reuse the given pointer for pinning.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmitry Osipenko [Thu, 15 Mar 2018 01:00:25 +0000 (04:00 +0300)]
drm/tegra: dc: Dedicate overlay plane to cursor on older Tegra's
Older Tegra's do not support RGBA format for the cursor, but instead
overlay plane could be used for it. Since there is no much use for the
overlays on a regular desktop and HW-accelerated cursor is much better
than a SW cursor, let's dedicate one overlay plane to the mouse cursor.
Feifei Xu [Wed, 7 Mar 2018 03:42:33 +0000 (22:42 -0500)]
drm/amdgpu/sdma4: Remove unused header file from sdma_v4_0.c
Remove mmhub header files inclusion which not used.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 1 Sep 2017 20:47:54 +0000 (16:47 -0400)]
drm/amdgpu/sdma4: use num_instances for clock/powergating config
Rather then relying on the asic type for the second instance.
Makes it more consistent with the rest of the code.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Colin Ian King [Tue, 13 Mar 2018 13:22:17 +0000 (13:22 +0000)]
drm/amd/pp: remove redundant pointer internal_buf
The pointer internal_buf is assigned a value but the pointer is never
read, hence it is redundant and can be removed.
Cleans up clang warning:
drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/smu7_smumgr.c:630:2:
warning: Value stored to 'internal_buf' is never read
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 9 Mar 2018 20:22:28 +0000 (15:22 -0500)]
drm/amdgpu/soc15: always load the psp module
Regardless of whether the user has selected psp fw loading or
not. It's still needed for GPU reset among other things.
There are already guards in place to avoid setting up the full
psp if PSP fw loading is not enabled.
Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Tue, 13 Mar 2018 06:25:11 +0000 (11:55 +0530)]
drm/amd/display: Check msg->size before starting aux transfer
This patch adds an essential check related to the size of the
payload to be transferred via aux channel.
Without this check dal_ddc_service_read_dpcd_data() is fed with
inappropriate payload size leading to deadlocks.
Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Mon, 5 Mar 2018 15:28:34 +0000 (10:28 -0500)]
drm/amd/display: Fixed dim around 1sec when resume from S3 (v2)
root cause:
DMCU try to perform a smoothness brightness change.Incorrect initial
brightness level causes the 1 sec dim.
Change:
Cache brightness level in stream, and clear it when edp backlight on.
If brightness level in stream is 0, set brightness with ramp value is 0.
DMCU will set the brightness without smoothness transition.
v2: squash in null pointer fix (Harry)
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Use actual TG instance instead of pipe instance
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Fri, 2 Mar 2018 22:19:27 +0000 (17:19 -0500)]
drm/amd/display: Check for HW blocks in HWSS, rather than DC core for cursor
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Wed, 28 Feb 2018 22:14:50 +0000 (17:14 -0500)]
drm/amd/display: Set disp clk in a safe way to avoid over high dpp clk. (v2)
Increase clock, if current dpp div is 0 and request dpp div is 1, request clk is
higher than maximum dpp clk as per dpm table.
set dispclk to the value of maximum supported dpp clk
set div to 1
set dispclk to request value.
Decrease clock, currrent dpp div is 1 and request dpp div is 0, current clk is
higher than maximum dpp clk as per dpm table.
set dispclk to the value of maximum supported dpp clk
set div to 0
set dispclk to request value.
v2: squash in !DCN build fix
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samson Tam [Thu, 1 Mar 2018 16:06:34 +0000 (11:06 -0500)]
drm/amd/display: add support for regkey "LCDFreeSyncDefault"
Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Tue, 27 Feb 2018 09:18:13 +0000 (14:48 +0530)]
drm/amd/display: Correct the plane enumeration order (v2)
The order of planes is given by the order they are enumerated
by kms.
Planes with a higher ID appears above planes with a lower ID.
Currently the planes are enumerated in the wrong order,
putting the nv12 only plane after the two RGBA planes.
This patch corrects the plane enumeration order such that all
the overlay planes are initialized first then the primary planes.
Due to this change in order the dc_add_plane_to_context() shall
receive the planes in reverse order hence this patch reverses
the parsing of planes in DM side itself.
v2: drop local reverse macro for upstream
Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Wed, 21 Feb 2018 21:41:19 +0000 (16:41 -0500)]
drm/amd/display: dal 3.1.38
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Wed, 28 Feb 2018 16:37:51 +0000 (11:37 -0500)]
drm/amd/display: Add variable refresh rate parameters to DC structures
Time stamping will be part of surface, and will be updated when address is flipped.
FreeSync parameters will be attached to stream, as it adjusts the timing dynamically.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Thu, 22 Feb 2018 14:50:25 +0000 (09:50 -0500)]
drm/amd/display: Implement stats logging
Stats will be used for debug purposes
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Wed, 28 Feb 2018 19:45:36 +0000 (14:45 -0500)]
drm/amd/display: early return if not in vga mode in disable_vga
The work around for hw bug causes S3 resume failure. Don't execute
disable vga logic if not in vga mode.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mikita Lipski [Tue, 27 Feb 2018 21:22:29 +0000 (16:22 -0500)]
drm/amd/display: Enable backlight support for pre-DCE11 ASICs
Initializing ABM and DMCU modules for dce 80/81/83/100 as in DCE110
Adding constructors and destructors for each module.
Adding register list for DMCU in dce80 as some registers are missing
in dce80 from the basic list. DMCU is never used, so it would not have
any functional impact.
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Krunoslav Kovac [Fri, 23 Feb 2018 22:51:33 +0000 (17:51 -0500)]
drm/amd/display: use HW hdr mult for brightness boost
In MPO scenario when playing SDR clip in HDR desktop mode, Win is
boosting desktop and requests driver to boost MPO. But driver boosting
is currently done in regamma which is stream property and thus shared
between grph and video.
Redesigning the boosting in RV: use CM_HDR_MULT register which was added
for this scenario. It also has the benefit that it can be done in HIRQL.
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Tue, 27 Feb 2018 20:06:31 +0000 (15:06 -0500)]
drm/amd/display: Modified set bandwidth sequence.
This change make sure bandwidth is set properly.
For increase bandwidth, set bandwidth before backend
and front end programming.
For decrease bandwidth, set bandwidth after.
To avoid smu hang when reboot and dpms due to 0 disp clk,
keep min disp clock as 100Mhz.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Tue, 27 Feb 2018 20:34:30 +0000 (15:34 -0500)]
drm/amd/display: fix check condition for edp power control
Per discussion with VBIOS team, the orginal check is not correct in
all cases on latest VBIOS. Additional check is needed. This change should
maintain old behaviour on older VBIOS.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
HW Engineer's Notes:
During switch from vga->extended, if we set the VGA_TEST_ENABLE and then
hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
VGA_TEST_ENABLE, to leave it in the same state as before.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
300Mhz disp clk limit was a workaround that was fixed in SMU and is no
longer needed.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Sunpeng) Li [Fri, 23 Feb 2018 17:59:03 +0000 (12:59 -0500)]
drm/amd/display: Convert CTM to 2's complement
DRM's documentation for the color transform matrix does not specify
whether the values are in signed-magnitude, or 2's complement.
Therefore, it was assumed to use 2's complement.
However, existing usermode implementations use signed-magnitude.
Therefore, conform to existing standards, and convert to 2's complement
internally.
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Varibright fix bug and review comments
Fix bug and make changes from review 132656
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Vari-bright looks disabled near end of MM14
Avoid hanging DMCU by setting abm level only when OTG unblanked
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Sunpeng) Li [Tue, 20 Feb 2018 21:03:48 +0000 (16:03 -0500)]
drm/amd/display: Use correct error codes
Should return -ENOMEM when allocation fails.
Also, just return the error code instead of using a variable.
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Sunpeng) Li [Tue, 20 Feb 2018 20:46:09 +0000 (15:46 -0500)]
drm/amd/display: Fix memleaks when atomic check fails.
While checking plane states for updates during atomic check, we create
dc_plane_states in preparation. These dc states should be freed if
something errors.
Although the input transfer function is also freed by
dc_plane_state_release(), we should free it (on error) under the same
scope as where it is created.
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Fri, 9 Mar 2018 01:44:15 +0000 (20:44 -0500)]
drm/amdgpu: Remove some unused elements from amdgpu_connector struct
They were used by amdgpu_dm at some point but since it has its own
amdgpu_dm_connector now these aren't needed anymore.
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 8 Mar 2018 14:56:01 +0000 (09:56 -0500)]
drm/amdgpu: save/restore backlight level in legacy dce code
Save/restore the backlight level scratch register in S3/S4 so the
backlight level comes back at the previously requested level.
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=199047 Fixes: 4ec6ecf48c64d (drm/amdgpu: drop scratch regs save and restore from S3/S4 handling) Acked-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 9 Mar 2018 13:44:32 +0000 (14:44 +0100)]
drm/radeon: fix prime teardown order
We unmapped imported DMA-bufs when the GEM handle was dropped, not when the
hardware was done with the buffere.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> CC: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 9 Mar 2018 13:42:54 +0000 (14:42 +0100)]
drm/amdgpu: fix prime teardown order
We unmapped imported DMA-bufs when the GEM handle was dropped, not when the
hardware was done with the buffere.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> CC: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 14 Mar 2018 19:48:17 +0000 (14:48 -0500)]
drm/amdgpu: explicit give BO type to amdgpu_bo_create
Drop the "kernel" and sg parameter and give the BO type to create
explicit to amdgpu_bo_create instead of figuring it out from the
parameters.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 20 Feb 2018 18:42:40 +0000 (19:42 +0100)]
drm/amdgpu: initial validate the prime BOs into the CPU domain
Just set the GTT domain as mandatory, so that the BO is validated into
it on first use. This allows us to setup the sg table later on.
Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 20 Feb 2018 18:09:56 +0000 (19:09 +0100)]
drm/amdgpu: drop the backing store when DMA-buf imports are evicted
Instead of moving this to the SYSTEM domain just drop the backing store
and let the resulting allocation be freed.
Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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