Alex Deucher [Wed, 28 Aug 2019 13:47:34 +0000 (08:47 -0500)]
drm/amdgpu/virtual_dce: drop error message in hw_init
No need to add new asic cases. This is a sw display
implementation, so just drop the error message so when
we add new asics, all we have to do is add the virtual
dce IP module.
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jean Delvare [Wed, 28 Aug 2019 15:05:57 +0000 (17:05 +0200)]
drm/amdgpu/si: fix ASIC tests
Comparing adev->family with CHIP constants is not correct.
adev->family can only be compared with AMDGPU_FAMILY constants and
adev->asic_type is the struct member to compare with CHIP constants.
They are separate identification spaces.
Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10") Cc: Ken Wang <Qingqing.Wang@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 27 Aug 2019 08:32:55 +0000 (16:32 +0800)]
drm/amdgpu: introduce vram lost for reset (v2)
for SOC15/vega10 the BACO reset & mode1 would introduce vram lost
in high end address range, current kmd's vram lost checking cannot
catch it since it only check very ahead visible frame buffer
v2:
cover NV as well
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Tue, 27 Aug 2019 14:59:45 +0000 (22:59 +0800)]
drm/amdgpu: fix GFXOFF on Picasso and Raven2
For picasso(adev->pdev->device == 0x15d8)&raven2(adev->rev_id >= 0x8),
firmware is sufficient to support gfxoff.
In commit 98f58ada2d37e, for picasso&raven2,
return directly and cause gfxoff disabled.
Fixes: 98f58ada2d37 ("drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possible") Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Masahiro Yamada [Tue, 27 Aug 2019 06:44:25 +0000 (15:44 +0900)]
drm/amd: remove meaningless descending into amd/amdkfd/
Since commit 04d5e2765802 ("drm/amdgpu: Merge amdkfd into amdgpu"),
drivers/gpu/drm/amd/amdkfd/Makefile does not contain any syntax that
is understood by the build system.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Tue, 27 Aug 2019 07:09:25 +0000 (15:09 +0800)]
drm/amd/display: remove unused function setFieldWithMask
After commit a9f54ce3c603 ("drm/amd/display: Refactoring VTEM"),
there is no caller in tree.
Reported-by: Hulk Robot <hulkci@huawei.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 19 Aug 2019 05:17:53 +0000 (13:17 +0800)]
drm/amd/powerplay: correct Vega20 dpm level related settings
Correct the settings for auto mode and skip the unnecessary
settings for dcefclk and fclk.
Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Implement HW I2C enigne controller to be used by the RAS EEPROM
table manager. This is based on code from ATITOOLs.
v2:
Rename the file and all function prefixes to smu_v11_0_i2c
By Luben's observation always fill the TX fifo to full so
we don't have garbadge interpreted by the slave as valid data.
v3:
Remove preemption disable as the HW I2C controller will not
stop the clock on empty TX fifo and so it's not critical to
keep not empty queue.
Switch to fast mode 400 khz SCL clock for faster read and write.
v5:
Restore clock gating before releasing I2C bus and fix some
style comments.
drm/amd/powerplay: Add interface to lock SMU HW I2C.
v2:
PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict
over I2C bus and engine disable thermal control access to
force SMU stop using the I2C bus until the issue is reslolved.
Expose and call vega20_is_smc_ram_running to skip locking when SMU
FW is not yet loaded.
v3:
Remove the prevoius hack as the SMU found the bug.
v5: Typo fix
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Mon, 26 Aug 2019 08:57:07 +0000 (16:57 +0800)]
drm/amdgpu/display: fix build error without CONFIG_DRM_AMD_DC_DSC_SUPPORT
If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28:
error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control?
dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
^~~~~~~~~~~~~~~~~~~~
dcn20_dpp_pg_control
Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this.
Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Mon, 26 Aug 2019 13:20:12 +0000 (16:20 +0300)]
drm/amd/powerplay: Fix an off by one in navi10_get_smu_msg_index()
The navi10_message_map[] array has SMU_MSG_MAX_COUNT elements so the ">"
has to be changed to ">=" to prevent reading one element beyond the end
of the array.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Since reservation_object_wait_timeout_rcu is called with
interruptable set to false it's wrong to say
'or interrupted' in the error message.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Fri, 16 Aug 2019 08:13:28 +0000 (16:13 +0800)]
drm/amdgpu: add dummy read for some GCVM status registers
The GRBM register interface is now capable of bursting 1 cycle per
register wr->wr, wr->rd much faster than previous muticycle per
transaction done interface. This has caused a problem where status
registers requiring HW to update have a 1 cycle delay, due to the
register update having to go through GRBM.
SW may operate on an incorrect value if they write a register and
immediately check the corresponding status register.
Registers requiring HW to clear or set fields may be delayed by 1 cycle.
For example,
1. write VM_INVALIDATE_ENG0_REQ mask = 5a
2. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a
a. HW will reset VM_INVALIDATE_ENG0_ACK = 0 until invalidation is complete
3. write VM_INVALIDATE_ENG0_REQ mask = 5a
4. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a
a. First read of VM_INVALIDATE_ENG0_ACK = 5a instead of 0
b. Second read of VM_INVALIDATE_ENG0_ACK = 0 because
the remote GRBM h/w register takes one extra cycle to be cleared
c. In this case, SW will see a false ACK if they exit on first read
hersen wu [Fri, 2 Aug 2019 20:01:37 +0000 (16:01 -0400)]
drm/amd/display: flicking observed while installing driver on Navi10 CF
[WHY] value of dchub_ref_clock is decided by dchubbub global timer
settings which is programmed by vbios command table disp_init.
for multi-GPU case, vbios is posted only for primary GPU. without
vbios posted for the secondary GPU, value of dchub_ref_clock is not
set properly. this value will affect dcn bandwidth calcuation and
cause underflow. user will see screen flicking during driver
installation for dual GPU case.
[HOW] dc init_hw always call vbios command table disp_init to
make sure dchubbub global timer is configured and enable.
Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joshua Aberback [Thu, 8 Aug 2019 17:22:36 +0000 (13:22 -0400)]
drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL
[Why]
The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the
embedded display. Currently we do not actually read this register's values,
so during power down we think that this display is already off, so we skip
calling into VBIOS to actually turn it off.
[How]
- add relevant fields to shift / mask initialization
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Tue, 23 Jul 2019 20:56:03 +0000 (16:56 -0400)]
drm/amd/display: revert wait in pipelock
[why]
Previous workaround to prevent a vsync flip to be converted
to immediate flip is no longer needed, and is risky because
there are cases where it can result in infinite loop.
[how]
Remove wait loop (which is potentially infinite) before locking
pipe
Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bayan Zabihiyan [Thu, 8 Aug 2019 15:08:52 +0000 (11:08 -0400)]
drm/amd/display: Expose OTG_V_TOTAL_MID for HW Diags
[Why]
Existing HW Features, HW Diags test requested that the
registers be exposed.
[How]
Add V_TOTAL_MID to existing DC structures.
Make sure values are passed down throughout DC
Add Register definition.
Program the additional registers
Add additional Logic for V_TOTAL_CONTROL.
Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Wed, 7 Aug 2019 20:24:46 +0000 (16:24 -0400)]
drm/amd/display: fix DML not calculating delivery time
[why]
Calculating DCFCLK DS time requires calculating
delivery time for luma/chroma, but this value is
not calculated in DMLv2, it was inadvertently
removed when porting DMLv2
[how]
Add the calculation back
Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Francis [Thu, 25 Jul 2019 19:22:16 +0000 (15:22 -0400)]
drm/amd/display: MST topology debugfs
DRM provides drm_dp_mst_dump_topology, which prints
useful information about MST devices
Hook this up to a debugfs file named amdgpu_mst_topology
Signed-off-by: David Francis <David.Francis@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Wed, 7 Aug 2019 21:25:49 +0000 (17:25 -0400)]
drm/amd/display: set av_mute in hw_init for HDMI
[Description]
OS will reserve HW state in UEFI mode.
Driver init_hw reset to RGB which caused HDMI green in YCbCr mode.
read HW blank_color based on acc_mode.
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jaehyun Chung [Wed, 7 Aug 2019 15:20:16 +0000 (11:20 -0400)]
drm/amd/display: Enable HW rotation
[Why] HW rotation is not enabled. Calculations for cursor rotation
are wrong for the values passed to set_cursor_position.
[How] Swap Src rect and height and vertically mirror surface for
the correct surface rotation direction. Cursor position is rotated
according to angle. Offset calculations are tweaked for non-rotated
cursor hotspot and width/height.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zi Yu Liao [Tue, 6 Aug 2019 15:58:09 +0000 (11:58 -0400)]
drm/amd/display: fix stuck test pattern on right half of display
[why]
With visual confirm enabled, displays where ODM combine is enabled
has a test pattern stuck on the right half of the display even
though the display is unblanked.
[how]
Add a condition to not show the colour ramp test pattern when the
display is unblanked.
Signed-off-by: Zi Yu Liao <ziyu.liao@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Fri, 2 Aug 2019 18:49:58 +0000 (14:49 -0400)]
drm/amd/display: support spdif
[Description]
port spdif fix to staging:
spdif hardwired to afmt inst 1.
spdif func pointer
spdif resource allocation (reserve last audio endpoint for spdif only)
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ahmad Othman [Thu, 1 Aug 2019 19:05:27 +0000 (15:05 -0400)]
drm/amd/display: Refactoring VTEM
[Why]
Video Timing Extended Metadata packet (VTEM) is not
specific to freesync. So move it out of freesync module
[How]
- Moved VTEM from freesync module to info_packet module
- Created new structure for VTEM parameters that can be used for VRR
and FVA
Signed-off-by: Ahmad Othman <ahmad.othman@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Ahmad Othman <Ahmad.Othman@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Leung [Fri, 2 Aug 2019 15:01:05 +0000 (11:01 -0400)]
drm/amd/display: cleaned up coding error in init_hw
[why]
during a refactor a redundant code that has unknown behaviour was added.
[how]
removed old bad code
Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Thu, 1 Aug 2019 19:52:58 +0000 (15:52 -0400)]
drm/amd/display: Zero-out dsc init regs
[why]
Before a statically allocated PPS data structure, that did
get zeroed-out at startup, had been re-used for making packed PPS
SDP. With S3 fix, using a non-initialized PPS data structure was
introduced, while wrongly assuming it'd get initialized before it's
populated. As a consequence 'vbr_enable' and perhaps some other
fields are left uninitialized when making packed PPS SDP. This can
affect 'simple_422' as well because of the way PPS SDP packing is
done (the fields are not masked first, only shifted). The behavior
will be different, depending on the content of uninitialized data.
[how]
Zero-out PPS data structure at initialization time before it's
populated
Fixes: 1a9e3d4569fc ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end") Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joseph Gravenor [Tue, 30 Jul 2019 20:37:35 +0000 (16:37 -0400)]
drm/amd/display: Implement voltage limitation stub
add new function to get the voltage at the end of
dcn_validate_bandwidth, to check against the
highest voltage we allow.
Created a stub to allow for optimizations
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Sun peng Li <Sunpeng.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Josip Pavic [Tue, 30 Jul 2019 20:56:14 +0000 (16:56 -0400)]
drm/amd/display: load iram for abm 2.3
[Why]
ABM 2.3 firmware expects information in iRAM that differs from previous
versions of ABM, so a mechanism is required to provide it with that
information.
[How]
Extend the existing iRAM definition to include parameters added by
ABM 2.3, and load it if DMCU is running ABM 2.3.
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: fix MPO HUBP underflow with Scatter Gather
[why]
With Scatter Gather enabled, HUBP underflows during MPO enabled video
playback. hubp_init has a register write that fixes this problem, but
the register is cleared when HUBP gets power gated.
[how]
Make a call to hubp_init during enable_plane, so that the fix can
be applied after HUBP powers back on again.
Signed-off-by: Zi Yu Liao <ziyu.liao@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: fix audio endpoint not getting disabled issue
[Why]
Disable_audio_stream gets enum option as a paramenter which will decide
if we free acquired resources or not. However checks for the option is
guarded by the other condition which check if audio stream is getting
diabled more than once. With both conditions combined, if we attempt to
disable audio stream twice in a row, first with keep and second with
free as an option, we will never free any resources, which will make
system think there is audio endpoint connected even after we plug out
the device
[How]
Get rid of option as parameter to disable_audio_stream and move the part
of the code that free acquired resources to outside where to keep or to
free resources is actually determined
Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Delete dead code in command_table_helper
[Why]
dig_encoder_sel_to_atom will always return zero on any ASIC version
past DCE80 since programming of the FE selection is handled by
driver, but the translation code was left in the function, making
it look like a coding error.
[How]
Remove code that has no effect, and replace with a comment describing
why it returns zero.
Signed-off-by: Julian Parkin <julian.parkin@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: re structure odm to allow 4 to 1 support
Currently odm is handled using top_bottom pipe by special casing
the differing opps to differentiate from mpc combine.
Since top/bottom pipe list was made to track mpc muxing this creates
difficulties in adding a 4 pipe odm case support.
Rather than continue using mpc combine list, this change reworks odm
to use it's own linked list to keep track of odm combine pipes. This
also opens up options for using mpo with odm, if a practical use case
is ever found.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 23 Aug 2019 14:42:33 +0000 (09:42 -0500)]
drm/amdgpu: set adev->num_vmhubs for gmc6,7,8
So that we properly handle them on older asics.
Fixes: 3ff985485b29 ("drm/amdgpu: Export function to flush TLB of specific vm hub") Tested-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 22 Aug 2019 19:17:57 +0000 (14:17 -0500)]
drm/amdgpu/display: add flag for multi-display mclk switching
Add a dcfeaturemask flag for mclk switching. Disable by default;
enable once the feature has seen more testing.
Set amdgpu.dcfeaturemask=2 on the kernel command line in grub
to enable this.
Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 23 Aug 2019 16:32:37 +0000 (11:32 -0500)]
drm/amd/display: update bw_calcs to take pipe sync into account (v3)
Properly set all_displays_in_sync so that when the data is
propagated to powerplay, it's set properly and we can enable
mclk switching when all monitors are in sync.
v2: fix logic, clean up
v3: check for blending chains, simplify logic
Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kent Russell [Fri, 23 Aug 2019 13:13:18 +0000 (09:13 -0400)]
drm/powerplay: Fix Vega20 power reading again
For the 40.46 SMU release, they changed CurrSocketPower to
AverageSocketPower, but this was changed back in 40.47 so just check if
it's 40.46 and make the appropriate change
Tested with 40.45, 40.46 and 40.47 successfully
Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Wed, 21 Aug 2019 02:58:19 +0000 (10:58 +0800)]
drm/amd/powerpaly: fix navi series custom peak level value error
fix other navi asic set peak performance level error.
because the navi10_ppt.c will handle navi12 14 asic,
it will use navi10 peak value to set other asic, it is not correct.
after patch:
only navi10 use custom peak value, other asic will used default value.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This was broken by a previous change switching to cached fw_info.
Fixed by inverting a valid bool check.
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111432 Fixes: 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create") Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This patch adds add DPMCLOCKS table implementation
Rename smu_populate_smc_pptable to smu_populate_smc_tables
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Tue, 30 Jul 2019 03:04:58 +0000 (11:04 +0800)]
drm/amd/powerplay: init smu tables for rn
Initialize smu tables for renoir:
WATERMARKS/DPMCLOCKS/SMU_METRICS
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Tue, 30 Jul 2019 02:50:44 +0000 (10:50 +0800)]
drm/amd/powerplay: add smu tables for rn
add and map smu tables for renoir
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Wed, 21 Aug 2019 21:45:52 +0000 (16:45 -0500)]
drm/amd/powerplay: using valid mapping check for rn
Check whether the message mapping is valid
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Fri, 26 Jul 2019 02:51:32 +0000 (10:51 +0800)]
drm/amd/powerplay: fix checking gfxoff status for rn
For renoir, it should use mmSMUIO_GFX_MISC_CNTL to check
gfxoff status. For the first time to enter gfxoff status,
it maybe takes about one second more. So just set the max
timeout to 5s.
GFXOFF_STATUS(bits 2:1)'s description is below:
0=GFXOFF(default).
1=Transition out of GFX State.
2=Not in GFXOFF.
3=Transition into GFXOFF.
Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Tue, 16 Jul 2019 09:33:47 +0000 (17:33 +0800)]
drm/amdgpu: add and enable gfxoff feature
This patch updates gfxoff feature.
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 8 Aug 2019 20:21:44 +0000 (15:21 -0500)]
drm/amdgpu/powerplay: add Renoir VCN power management
Thus VCN can be powered up for normal operations
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>