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5 years agommc: mtk-sd: don't hard-code interrupt trigger type
NeilBrown [Sat, 4 May 2019 10:24:56 +0000 (20:24 +1000)]
mmc: mtk-sd: don't hard-code interrupt trigger type

When using devicetree for configuration, interrupt trigger type
should be described in the dts file, not hard-coded in the C code.

The mtk-sd silicon in the mt7621 soc uses an active-high interrupt
and so cannot be used with the current code.

So replace IRQF_TRIGGER_LOW with IRQF_TRIGGER_NONE.

Also IRQF_ONESHOT is not needed - it is used for threaded interrupt
handlers, and this driver does not used a threaded interrupt handler.
So remove that setting.

Signed-off-by: NeilBrown <neil@brown.name>
Reviewed-by: Chaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: core: Fix tag set memory leak
Raul E Rangel [Thu, 2 May 2019 19:07:14 +0000 (13:07 -0600)]
mmc: core: Fix tag set memory leak

The tag set is allocated in mmc_init_queue but never freed. This results
in a memory leak. This change makes sure we free the tag set when the
queue is also freed.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Jens Axboe <axboe@kernel.dk>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Fixes: 81196976ed94 ("mmc: block: Add blk-mq support")
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agodt-bindings: mmc: Add support for MT8516 to mtk-sd
Fabien Parent [Sat, 23 Mar 2019 21:15:56 +0000 (22:15 +0100)]
dt-bindings: mmc: Add support for MT8516 to mtk-sd

Add binding documentation of mtk-sd for MT8516 SoCs.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: mmci: Prevent polling for busy detection in IRQ context
Ludovic Barre [Fri, 26 Apr 2019 07:46:35 +0000 (09:46 +0200)]
mmc: mmci: Prevent polling for busy detection in IRQ context

The IRQ handler, mmci_irq(), loops until all status bits have been cleared.
However, the status bit signaling busy in variant->busy_detect_flag, may be
set even if busy detection isn't monitored for the current request.

This may be the case for the CMD11 when switching the I/O voltage, which
leads to that mmci_irq() busy loops in IRQ context. Fix this problem, by
clearing the status bit for busy, before continuing to validate the
condition for the loop. This is safe, because the busy status detection has
already been taken care of by mmci_cmd_irq().

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: mmci: Cleanup mmci_cmd_irq() for busy detect
Ludovic Barre [Fri, 26 Apr 2019 07:46:34 +0000 (09:46 +0200)]
mmc: mmci: Cleanup mmci_cmd_irq() for busy detect

Let's cleanup the mmci_cmd_irq() a bit, to make the busy detect code more
clear.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: usdhi6rol0: mark expected switch fall-throughs
Gustavo A. R. Silva [Wed, 1 May 2019 20:36:21 +0000 (15:36 -0500)]
mmc: usdhi6rol0: mark expected switch fall-throughs

In preparation to enabling -Wimplicit-fallthrough, mark switch
cases where we are expecting to fall through.

This patch fixes the following warnings:

In file included from drivers/mmc/host/usdhi6rol0.c:9:
drivers/mmc/host/usdhi6rol0.c: In function ‘usdhi6_timeout_work’:
./include/linux/device.h:1483:2: warning: this statement may fall through [-Wimplicit-fallthrough=]
  _dev_err(dev, dev_fmt(fmt), ##__VA_ARGS__)
  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/mmc/host/usdhi6rol0.c:1689:3: note: in expansion of macro ‘dev_err’
   dev_err(mmc_dev(host->mmc), "Invalid state %u\n", host->wait);
   ^~~~~~~
drivers/mmc/host/usdhi6rol0.c:1691:2: note: here
  case USDHI6_WAIT_FOR_CMD:
  ^~~~
drivers/mmc/host/usdhi6rol0.c:1711:3: warning: this statement may fall through [-Wimplicit-fallthrough=]
   usdhi6_sg_unmap(host, true);
   ^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/mmc/host/usdhi6rol0.c:1716:2: note: here
  case USDHI6_WAIT_FOR_DATA_END:
  ^~~~
  CC [M]  drivers/isdn/hisax/hisax_isac.o
drivers/mmc/host/usdhi6rol0.c: In function ‘usdhi6_stop_cmd’:
drivers/mmc/host/usdhi6rol0.c:1338:6: warning: this statement may fall through [-Wimplicit-fallthrough=]
   if (mrq->stop->opcode == MMC_STOP_TRANSMISSION) {
      ^
drivers/mmc/host/usdhi6rol0.c:1343:2: note: here
  default:
  ^~~~~~~

Warning level 3 was used: -Wimplicit-fallthrough=3

This patch is part of the ongoing efforts to enable
-Wimplicit-fallthrough.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: core: Verify SD bus width
Raul E Rangel [Mon, 29 Apr 2019 17:32:39 +0000 (11:32 -0600)]
mmc: core: Verify SD bus width

The SD Physical Layer Spec says the following: Since the SD Memory Card
shall support at least the two bus modes 1-bit or 4-bit width, then any SD
Card shall set at least bits 0 and 2 (SD_BUS_WIDTH="0101").

This change verifies the card has specified a bus width.

AMD SDHC Device 7806 can get into a bad state after a card disconnect
where anything transferred via the DATA lines will always result in a
zero filled buffer. Currently the driver will continue without error if
the HC is in this condition. A block device will be created, but reading
from it will result in a zero buffer. This makes it seem like the SD
device has been erased, when in actuality the data is never getting
copied from the DATA lines to the data buffer.

SCR is the first command in the SD initialization sequence that uses the
DATA lines. By checking that the response was invalid, we can abort
mounting the card.

Reviewed-by: Avri Altman <avri.altman@wdc.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP
BOUGH CHEN [Mon, 29 Apr 2019 08:55:43 +0000 (08:55 +0000)]
mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP

Add HS400 support for iMX7ULP B0.

According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET
before any setting of STROBE_DLL_CTRL register.

USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL)
for slave sel value. If this register bits value is 0,  it needs
256 ref_clk cycles to update slave sel value. IC suggest to set
bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave
sel value. This will short the lock time of slave.

i.MX7ULP B0 will need more time to lock the REF and SLV, so change
to add 5us delay.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: sdhci-esdhc-imx: add pm_qos to interact with cpuidle
BOUGH CHEN [Mon, 29 Apr 2019 08:55:37 +0000 (08:55 +0000)]
mmc: sdhci-esdhc-imx: add pm_qos to interact with cpuidle

On some SoCs such as i.MX7ULP, there is no busfreq
driver, but cpuidle has some levels which may disable
system/bus clocks, so need to add pm_qos to prevent
cpuidle from entering low level idles and make sure
system/bus clocks are enabled when usdhc is active.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agodt-bindings: mmc: fsl-imx-esdhc: add imx7ulp compatible string
BOUGH CHEN [Mon, 29 Apr 2019 08:55:32 +0000 (08:55 +0000)]
dt-bindings: mmc: fsl-imx-esdhc: add imx7ulp compatible string

Add imx7ulp compatible string.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: meson-gx: add signal resampling tuning
Jerome Brunet [Tue, 23 Apr 2019 09:02:35 +0000 (11:02 +0200)]
mmc: meson-gx: add signal resampling tuning

Use signal resampling tuning for the UHS and HS200 modes.
Instead of trying to get the *best* resampling setting with complex
window calculation, we just stop on the first working setting.

If the tuning setting later proves unstable, we will just continue the
tuning where we left it.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: meson-gx: remove Rx phase tuning
Jerome Brunet [Tue, 23 Apr 2019 09:02:34 +0000 (11:02 +0200)]
mmc: meson-gx: remove Rx phase tuning

This remove all the code related to phase settings. Using the Rx phase
for tuning has not been reliable. We had several issues over the past
months, on both v2 and v3 mmc chips After discussing the issue matter
with Amlogic, They suggested to set a phase shift of 180 between Core and
Tx and use signal resampling for the tuning.

Since we won't be playing with the phase anymore, let's remove all the
clock code related to it and set the appropriate value on init.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: meson-gx: avoid clock glitch when switching to DDR modes
Jerome Brunet [Tue, 23 Apr 2019 09:02:33 +0000 (11:02 +0200)]
mmc: meson-gx: avoid clock glitch when switching to DDR modes

Activating DDR in the Amlogic mmc controller, among other things, will
divide the output clock by 2. So by activating it with clock on, we are
creating a glitch on the output.

Instead, let's deal with DDR when the clock output is off, when setting
the clock.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: meson-gx: disable HS400
Jerome Brunet [Tue, 23 Apr 2019 09:02:32 +0000 (11:02 +0200)]
mmc: meson-gx: disable HS400

At the moment, all our attempts to enable HS400 on Amlogic chipsets have
been unsuccessful or unreliable. Until we can figure out how to enable this
mode safely and reliably, let's force it off.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: meson-gx: correct irq flag
Jerome Brunet [Tue, 23 Apr 2019 09:02:31 +0000 (11:02 +0200)]
mmc: meson-gx: correct irq flag

There is no reason for another device to request the MMC irq. It should
only be used the MMC device, so remove IRQ_SHARED and replace by
IRQ_ONESHOT as we don't the irq to fire again until the irq thread is
done

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: meson-gx: ack only raised irq
Jerome Brunet [Tue, 23 Apr 2019 09:02:30 +0000 (11:02 +0200)]
mmc: meson-gx: ack only raised irq

This is merely a clean up. It makes sense to only ack raised irqs
instead of acking everything all the time.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: meson-gx: remove open coded read with timeout
Jerome Brunet [Tue, 23 Apr 2019 09:02:29 +0000 (11:02 +0200)]
mmc: meson-gx: remove open coded read with timeout

There is already a function available to poll a register until a
condition is met. Let's use it instead of open coding it.

Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: omap_hsmmc: Use dev_get_drvdata()
Kefeng Wang [Tue, 23 Apr 2019 07:50:12 +0000 (15:50 +0800)]
mmc: omap_hsmmc: Use dev_get_drvdata()

Using dev_get_drvdata directly.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: alcor: work with multiple-entry sglists
Daniel Drake [Mon, 29 Apr 2019 05:14:26 +0000 (13:14 +0800)]
mmc: alcor: work with multiple-entry sglists

DMA on this hardware is limited to dealing with a 4096 bytes at a
time. Previously, the driver was set up accordingly to request single-page
DMA buffers, however that had the effect of generating a large number
of small MMC requests for data I/O.

Improve the driver to accept multi-entry scatter-gather lists. The size of
each entry is already capped to 4096 bytes (AU6601_MAX_DMA_BLOCK_SIZE),
matching the hardware requirements. Existing driver code already iterates
through remaining sglist entries after each DMA transfer is complete.

Also add some comments to help clarify the situation, and clear up
some of the confusion I had regarding DMA vs PIO.

Testing with dd, this increases write performance from 2mb/sec to
10mb/sec, and increases read performance from 4mb/sec to 14mb/sec.

Signed-off-by: Daniel Drake <drake@endlessm.com>
Link: http://lkml.kernel.org/r/CAD8Lp47JYdZzbV9F+asNwvSfLF_po_J7ir6R_Vb-Dab21_=Krw@mail.gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agoRevert "mmc: alcor: enable DMA transfer of large buffers"
Daniel Drake [Mon, 29 Apr 2019 05:14:25 +0000 (13:14 +0800)]
Revert "mmc: alcor: enable DMA transfer of large buffers"

This reverts commit 57ebb96c293da9f0ec56aba13c5541269a5c10b1.

Usage of the DMA page iterator was problematic here because
we were not considering offset & length of entries in the scatterlist.

Also, after further discussion, the suggested revised approach is much
more similar to the driver implementation before this commit was
applied, so revert it.

Signed-off-by: Daniel Drake <drake@endlessm.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agomemstick: tifm: remove set but not used variable 'data'
YueHaibing [Thu, 25 Apr 2019 02:03:32 +0000 (02:03 +0000)]
memstick: tifm: remove set but not used variable 'data'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/memstick/host/tifm_ms.c: In function 'tifm_ms_issue_cmd':
drivers/memstick/host/tifm_ms.c:259:17: warning:
 variable 'data' set but not used [-Wunused-but-set-variable]

It's not used any more since commit 92b22d935fed ("tifm: fix the
MemoryStick host fifo handling code")

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agommc: core: fix possible use after free of host
Pan Bian [Wed, 17 Apr 2019 08:28:37 +0000 (16:28 +0800)]
mmc: core: fix possible use after free of host

In the function mmc_alloc_host, the function put_device is called to
release allocated resources when mmc_gpio_alloc fails. Finally, the
function pointed by host->class_dev.class->dev_release (i.e.,
mmc_host_classdev_release) is used to release resources including the
host structure. However, after put_device, host is used and released
again. Resulting in a use-after-free bug.

Fixes: 1ed217194488 ("mmc: core: fix error path in mmc_host_alloc")
Signed-off-by: Pan Bian <bianpan2016@163.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agoDocumentation/features/time: Mark m68k having modern-timekeeping
Geert Uytterhoeven [Mon, 6 May 2019 08:46:41 +0000 (10:46 +0200)]
Documentation/features/time: Mark m68k having modern-timekeeping

M68k no longer uses arch_gettimeoffset.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
5 years agoMerge branches 'pm-devfreq' and 'pm-domains'
Rafael J. Wysocki [Mon, 6 May 2019 08:55:49 +0000 (10:55 +0200)]
Merge branches 'pm-devfreq' and 'pm-domains'

* pm-devfreq:
  PM / devfreq: add tracing for scheduling work
  trace: events: add devfreq trace event file
  PM / devfreq: rk3399_dmc: Pass ODT and auto power down parameters to TF-A.
  PM / devfreq: rockchip-dfi: Move GRF definitions to a common place.
  PM / devfreq: exynos-bus: Suspend all devices on system shutdown
  PM / devfreq: Fix static checker warning in try_then_request_governor
  PM / devfreq: Restart previous governor if new governor fails to start
  PM / devfreq: tegra: remove unneeded variable
  PM / devfreq: rockchip-dfi: remove unneeded semicolon
  PM / devfreq: rk3399_dmc: remove unneeded semicolon
  PM / devfreq: consistent indentation
  PM / devfreq: fix missing check of return value in devfreq_add_device()
  PM / devfreq: fix mem leak in devfreq_add_device()
  PM / devfreq: Use of_node_name_eq for node name comparisons

* pm-domains:
  PM / Domains: Allow to attach a CPU via genpd_dev_pm_attach_by_id|name()
  PM / Domains: Search for the CPU device outside the genpd lock
  PM / Domains: Drop unused in-parameter to some genpd functions
  PM / Domains: Use the base device for driver_deferred_probe_check_state()
  PM / Domains: Enable genpd_dev_pm_attach_by_id|name() for single PM domain
  PM / Domains: Allow OF lookup for multi PM domain case from ->attach_dev()
  PM / Domains: Don't kfree() the virtual device in the error path
  PM / Domains: remove unnecessary unlikely()

5 years agoMerge branches 'pm-docs' and 'pm-misc'
Rafael J. Wysocki [Mon, 6 May 2019 08:55:19 +0000 (10:55 +0200)]
Merge branches 'pm-docs' and 'pm-misc'

* pm-docs:
  Documentation: PM: Unify copyright notices
  Documentation: PM: Add SPDX license tags to multiple files
  cpufreq: intel_pstate: Documentation: Add references sections

* pm-misc:
  firmware/psci: add support for SYSTEM_RESET2
  drivers: firmware: psci: Announce support for OS initiated suspend mode
  drivers: firmware: psci: Simplify error path of psci_dt_init()
  drivers: firmware: psci: Split psci_dt_cpu_init_idle()
  MAINTAINERS: Update files for PSCI
  drivers: firmware: psci: Move psci to separate directory

5 years agoMerge branches 'pm-cpuidle' and 'pm-sleep'
Rafael J. Wysocki [Mon, 6 May 2019 08:54:43 +0000 (10:54 +0200)]
Merge branches 'pm-cpuidle' and 'pm-sleep'

* pm-cpuidle:
  PM / Domains: Add genpd governor for CPUs
  cpuidle: Export the next timer expiration for CPUs
  PM / Domains: Add support for CPU devices to genpd
  PM / Domains: Add generic data pointer to struct genpd_power_state
  cpuidle: exynos: Unify target residency for AFTR and coupled AFTR states

* pm-sleep:
  PM / core: Propagate dev->power.wakeup_path when no callbacks
  PM / core: Introduce dpm_async_fn() helper
  PM / core: fix kerneldoc comment for device_pm_wait_for_dev()
  PM / core: fix kerneldoc comment for dpm_watchdog_handler()
  PM / sleep: Measure the time of filesystems syncing
  PM / sleep: Refactor filesystems sync to reduce duplication
  PM / wakeup: Use pm_pr_dbg() instead of pr_debug()

5 years agoMerge branch 'pm-cpufreq'
Rafael J. Wysocki [Mon, 6 May 2019 08:54:27 +0000 (10:54 +0200)]
Merge branch 'pm-cpufreq'

* pm-cpufreq: (24 commits)
  cpufreq: Fix kobject memleak
  cpufreq: armada-37xx: fix frequency calculation for opp
  cpufreq: centrino: Fix centrino_setpolicy() kerneldoc comment
  cpufreq: qoriq: add support for lx2160a
  cpufreq: qoriq: Add ls1028a chip support
  cpufreq: Move ->get callback check outside of __cpufreq_get()
  cpufreq: Remove needless bios_limit check in show_bios_limit()
  drivers/cpufreq/acpi-cpufreq.c: This fixes the following checkpatch warning
  cpufreq: boost: Remove CONFIG_CPU_FREQ_BOOST_SW Kconfig option
  cpufreq: stats: Use lock by stat to replace global spin lock
  cpufreq: Remove cpufreq_driver check in cpufreq_boost_supported()
  cpufreq: maple: Remove redundant code from maple_cpufreq_init()
  cpufreq: ppc_cbe: fix possible object reference leak
  cpufreq: pmac32: fix possible object reference leak
  cpufreq/pasemi: fix possible object reference leak
  cpufreq: maple: fix possible object reference leak
  cpufreq: kirkwood: fix possible object reference leak
  cpufreq: imx6q: fix possible object reference leak
  cpufreq: ap806: fix possible object reference leak
  drivers/cpufreq: Convert some slow-path static_cpu_has() callers to boot_cpu_has()
  ...

5 years agoMerge branch 'pm-x86'
Rafael J. Wysocki [Mon, 6 May 2019 08:54:07 +0000 (10:54 +0200)]
Merge branch 'pm-x86'

* pm-x86:
  x86: tsc: Rework time_cpufreq_notifier()
  admin-guide: pm: intel_epb: Add SPDX license tag and copyright notice
  PM / arch: x86: MSR_IA32_ENERGY_PERF_BIAS sysfs interface
  PM / arch: x86: Rework the MSR_IA32_ENERGY_PERF_BIAS handling

5 years agoMerge branch 'acpi-doc'
Rafael J. Wysocki [Mon, 6 May 2019 08:50:21 +0000 (10:50 +0200)]
Merge branch 'acpi-doc'

* acpi-doc: (25 commits)
  Documentation: ACPI: move video_extension.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move ssdt-overlays.txt to admin-guide/acpi and convert to reST
  Documentation: ACPI: move lpit.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move cppc_sysfs.txt to admin-guide/acpi and convert to reST
  Documentation: ACPI: move apei/einj.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move apei/output_format.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move aml-debugger.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move method-tracing.txt to firmware-guide/acpi and convert to rsST
  Documentation: ACPI: move debug.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move dsd/data-node-references.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move dsd/graph.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move acpi-lid.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move i2c-muxes.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move dsdt-override.txt to admin-guide/acpi and convert to reST
  Documentation: ACPI: move initrd_table_override.txt to admin-guide/acpi and convert to reST
  Documentation: ACPI: move method-customizing.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move gpio-properties.txt to firmware-guide/acpi and convert to reST
  Documentation: ACPI: move DSD-properties-rules.txt to firmware-guide/acpi and covert to reST
  Documentation: ACPI: move scan_handlers.txt to driver-api/acpi and convert to reST
  Documentation: ACPI: move linuxized-acpica.txt to driver-api/acpi and convert to reST
  ...

5 years agoMerge branches 'acpi-utils', 'acpi-video', 'acpi-soc' and 'acpi-button'
Rafael J. Wysocki [Mon, 6 May 2019 08:50:08 +0000 (10:50 +0200)]
Merge branches 'acpi-utils', 'acpi-video', 'acpi-soc' and 'acpi-button'

* acpi-utils:
  gpio: merrifield: Fix build err without CONFIG_ACPI
  ACPI / utils: Remove deprecated function since no user left
  ASoC: Intel: cht_bsw_rt5672: Convert to use acpi_dev_get_first_match_dev()
  ASoC: Intel: cht_bsw_rt5645: Convert to use acpi_dev_get_first_match_dev()
  ASoC: Intel: bytcr_rt5651: Convert to use acpi_dev_get_first_match_dev()
  ASoC: Intel: bytcr_rt5640: Convert to use acpi_dev_get_first_match_dev()
  ASoC: Intel: bytcht_es8316: Convert to use acpi_dev_get_first_match_dev()
  ASoC: Intel: bytcht_da7213: Convert to use acpi_dev_get_first_match_dev()
  gpio: merrifield: Convert to use acpi_dev_get_first_match_dev()
  extcon: axp288: Convert to use acpi_dev_get_first_match_dev()
  ACPI / utils: Introduce acpi_dev_get_first_match_dev() helper

* acpi-video:
  ACPI: video: Use vendor backlight on Sony VPCEH3U1E

* acpi-soc:
  ACPI / LPSS: Use acpi_lpss_* instead of acpi_subsys_* functions for hibernate

* acpi-button:
  ACPI: button: reinitialize button state upon resume

5 years agoMerge branches 'acpi-scan', 'acpi-tables', 'acpi-misc' and 'acpi-pm'
Rafael J. Wysocki [Mon, 6 May 2019 08:49:39 +0000 (10:49 +0200)]
Merge branches 'acpi-scan', 'acpi-tables', 'acpi-misc' and 'acpi-pm'

* acpi-scan:
  ACPI / scan: Add labels for PNP button devices
  ACPI / scan: Simplify acpi_bus_extract_wakeup_device_power_package()

* acpi-tables:
  ACPI / tables: Clean up whitespace

* acpi-misc:
  ACPI / DPTF: Use dev_get_drvdata()
  ACPI: event: replace strcpy() by strscpy()
  ACPI: Fix comment typos

* acpi-pm:
  ACPI: PM: Print debug messages when enabling GPEs for wakeup

5 years agoMerge branch 'acpica'
Rafael J. Wysocki [Mon, 6 May 2019 08:49:01 +0000 (10:49 +0200)]
Merge branch 'acpica'

* acpica:
  ACPICA: Update version to 20190405
  ACPICA: Namespace: add check to avoid null pointer dereference
  ACPICA: Update version to 20190329
  ACPICA: utilities: fix spelling of PCC to platform_comm_channel
  ACPICA: Rename nameseg length macro/define for clarity
  ACPICA: Rename nameseg compare macro for clarity
  ACPICA: Rename nameseg copy macro for clarity

5 years agoMerge branch 'for-5.2-pf-removal' into for-linus
Petr Mladek [Mon, 6 May 2019 08:33:10 +0000 (10:33 +0200)]
Merge branch 'for-5.2-pf-removal' into for-linus

5 years agoMerge branch 'for-5.2-vsprintf-hardening' into for-linus
Petr Mladek [Mon, 6 May 2019 08:32:45 +0000 (10:32 +0200)]
Merge branch 'for-5.2-vsprintf-hardening' into for-linus

5 years agox86/fpu: Fault-in user stack if copy_fpstate_to_sigframe() fails
Sebastian Andrzej Siewior [Thu, 2 May 2019 17:11:39 +0000 (19:11 +0200)]
x86/fpu: Fault-in user stack if copy_fpstate_to_sigframe() fails

In the compacted form, XSAVES may save only the XMM+SSE state but skip
FP (x87 state).

This is denoted by header->xfeatures = 6. The fastpath
(copy_fpregs_to_sigframe()) does that but _also_ initialises the FP
state (cwd to 0x37f, mxcsr as we do, remaining fields to 0).

The slowpath (copy_xstate_to_user()) leaves most of the FP
state untouched. Only mxcsr and mxcsr_flags are set due to
xfeatures_mxcsr_quirk(). Now that XFEATURE_MASK_FP is set
unconditionally, see

  04944b793e18 ("x86: xsave: set FP, SSE bits in the xsave header in the user sigcontext"),

on return from the signal, random garbage is loaded as the FP state.

Instead of utilizing copy_xstate_to_user(), fault-in the user memory
and retry the fast path. Ideally, the fast path succeeds on the second
attempt but may be retried again if the memory is swapped out due
to memory pressure. If the user memory can not be faulted-in then
get_user_pages() returns an error so we don't loop forever.

Fault in memory via get_user_pages_unlocked() so
copy_fpregs_to_sigframe() succeeds without a fault.

Fixes: 69277c98f5eef ("x86/fpu: Always store the registers in copy_fpstate_to_sigframe()")
Reported-by: Kurt Kanzenbach <kurt.kanzenbach@linutronix.de>
Suggested-by: Dave Hansen <dave.hansen@intel.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jann Horn <jannh@google.com>
Cc: "linux-mm@kvack.org" <linux-mm@kvack.org>
Cc: Qian Cai <cai@lca.pw>
Cc: Rik van Riel <riel@surriel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20190502171139.mqtegctsg35cir2e@linutronix.de
5 years agoi3c: Fix a shift wrap bug in i3c_bus_set_addr_slot_status()
Dan Carpenter [Tue, 23 Apr 2019 10:40:20 +0000 (13:40 +0300)]
i3c: Fix a shift wrap bug in i3c_bus_set_addr_slot_status()

The problem here is that addr can be I3C_BROADCAST_ADDR (126).  That
means we're shifting by (126 * 2) % 64 which is 60.  The
I3C_ADDR_SLOT_STATUS_MASK is an enum which is an unsigned int in GCC
so shifts greater than 31 are undefined.

Fixes: 3a379bbcea0a ("i3c: Add core I3C infrastructure")
Cc: <stable@vger.kernel.org>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
5 years agoLinux 5.1 v5.1
Linus Torvalds [Mon, 6 May 2019 00:42:58 +0000 (17:42 -0700)]
Linux 5.1

5 years agoparisc: Add static branch and JUMP_LABEL feature
Helge Deller [Fri, 3 May 2019 21:51:00 +0000 (23:51 +0200)]
parisc: Add static branch and JUMP_LABEL feature

Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Use PA_ASM_LEVEL in boot code
Helge Deller [Sun, 5 May 2019 21:55:02 +0000 (23:55 +0200)]
parisc: Use PA_ASM_LEVEL in boot code

The LEVEL define clashed with the DRBD code.

Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Helge Deller <deller@gmx.de>
Cc: <stable@vger.kernel.org> # v4.14+
5 years agoparisc: Rename LEVEL to PA_ASM_LEVEL to avoid name clash with DRBD code
Helge Deller [Sun, 5 May 2019 21:54:34 +0000 (23:54 +0200)]
parisc: Rename LEVEL to PA_ASM_LEVEL to avoid name clash with DRBD code

LEVEL is a very common word, and now after many years it suddenly
clashed with another LEVEL define in the DRBD code.
Rename it to PA_ASM_LEVEL instead.

Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Helge Deller <deller@gmx.de>
Cc: <stable@vger.kernel.org>
5 years agoMerge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 5 May 2019 21:37:25 +0000 (14:37 -0700)]
Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf fixes from Ingo Molnar:
 "I'd like to apologize for this very late pull request: I was dithering
  through the week whether to send the fixes, and then yesterday Jiri's
  crash fix for a regression introduced in this cycle clearly marked
  perf/urgent as 'must merge now'.

  Most of the commits are tooling fixes, plus there's three kernel fixes
  via four commits:

    - race fix in the Intel PEBS code

    - fix an AUX bug and roll back a previous attempt

    - fix AMD family 17h generic HW cache-event perf counters

  The largest diffstat contribution comes from the AMD fix - a new event
  table is introduced, which is a fairly low risk change but has a large
  linecount"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86/intel: Fix race in intel_pmu_disable_event()
  perf/x86/intel/pt: Remove software double buffering PMU capability
  perf/ring_buffer: Fix AUX software double buffering
  perf tools: Remove needless asm/unistd.h include fixing build in some places
  tools arch uapi: Copy missing unistd.h headers for arc, hexagon and riscv
  tools build: Add -ldl to the disassembler-four-args feature test
  perf cs-etm: Always allocate memory for cs_etm_queue::prev_packet
  perf cs-etm: Don't check cs_etm_queue::prev_packet validity
  perf report: Report OOM in status line in the GTK UI
  perf bench numa: Add define for RUSAGE_THREAD if not present
  tools lib traceevent: Change tag string for error
  perf annotate: Fix build on 32 bit for BPF annotation
  tools uapi x86: Sync vmx.h with the kernel
  perf bpf: Return value with unlocking in perf_env__find_btf()
  MAINTAINERS: Include vendor specific files under arch/*/events/*
  perf/x86/amd: Update generic hardware cache events for Family 17h

5 years agoMerge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 5 May 2019 21:28:48 +0000 (14:28 -0700)]
Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull scheduler fix from Ingo Molnar:
 "Fix a kobject memory leak in the cpufreq code"

* 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  sched/cpufreq: Fix kobject memleak

5 years agoMerge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 5 May 2019 21:26:11 +0000 (14:26 -0700)]
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 fix from Ingo Molnar:
 "Disable function tracing during early SME setup to fix a boot crash on
  SME-enabled kernels running distro kernels (some of which have
  function tracing enabled)"

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mm/mem_encrypt: Disable all instrumentation for early SME setup

5 years agox86/mm: Initialize PGD cache during mm initialization
Nadav Amit [Sun, 5 May 2019 01:11:24 +0000 (18:11 -0700)]
x86/mm: Initialize PGD cache during mm initialization

Poking-mm initialization might require to duplicate the PGD in early
stage. Initialize the PGD cache earlier to prevent boot failures.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Nadav Amit <namit@vmware.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rick Edgecombe <rick.p.edgecombe@intel.com>
Cc: Rik van Riel <riel@surriel.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Thomas Gleixner <tglx@linutronix.de>
Fixes: 4fc19708b165 ("x86/alternatives: Initialize temporary mm for patching")
Link: http://lkml.kernel.org/r/20190505011124.39692-1-namit@vmware.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
5 years agoMerge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
Linus Torvalds [Sun, 5 May 2019 16:28:45 +0000 (09:28 -0700)]
Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

Pull vfs fixes from Al Viro:

 - a couple of ->i_link use-after-free fixes

 - regression fix for wrong errno on absent device name in mount(2)
   (this cycle stuff)

 - ancient UFS braino in large GID handling on Solaris UFS images (bogus
   cut'n'paste from large UID handling; wrong field checked to decide
   whether we should look at old (16bit) or new (32bit) field)

* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
  ufs: fix braino in ufs_get_inode_gid() for solaris UFS flavour
  Abort file_remove_privs() for non-reg. files
  [fix] get rid of checking for absent device name in vfs_get_tree()
  apparmorfs: fix use-after-free on symlink traversal
  securityfs: fix use-after-free on symlink traversal

5 years agoperf/x86/intel: Fix race in intel_pmu_disable_event()
Jiri Olsa [Sat, 4 May 2019 15:15:56 +0000 (17:15 +0200)]
perf/x86/intel: Fix race in intel_pmu_disable_event()

New race in x86_pmu_stop() was introduced by replacing the
atomic __test_and_clear_bit() of cpuc->active_mask by separate
test_bit() and __clear_bit() calls in the following commit:

  3966c3feca3f ("x86/perf/amd: Remove need to check "running" bit in NMI handler")

The race causes panic for PEBS events with enabled callchains:

  BUG: unable to handle kernel NULL pointer dereference at 0000000000000000
  ...
  RIP: 0010:perf_prepare_sample+0x8c/0x530
  Call Trace:
   <NMI>
   perf_event_output_forward+0x2a/0x80
   __perf_event_overflow+0x51/0xe0
   handle_pmi_common+0x19e/0x240
   intel_pmu_handle_irq+0xad/0x170
   perf_event_nmi_handler+0x2e/0x50
   nmi_handle+0x69/0x110
   default_do_nmi+0x3e/0x100
   do_nmi+0x11a/0x180
   end_repeat_nmi+0x16/0x1a
  RIP: 0010:native_write_msr+0x6/0x20
  ...
   </NMI>
   intel_pmu_disable_event+0x98/0xf0
   x86_pmu_stop+0x6e/0xb0
   x86_pmu_del+0x46/0x140
   event_sched_out.isra.97+0x7e/0x160
  ...

The event is configured to make samples from PEBS drain code,
but when it's disabled, we'll go through NMI path instead,
where data->callchain will not get allocated and we'll crash:

          x86_pmu_stop
            test_bit(hwc->idx, cpuc->active_mask)
            intel_pmu_disable_event(event)
            {
              ...
              intel_pmu_pebs_disable(event);
              ...

EVENT OVERFLOW ->  <NMI>
                     intel_pmu_handle_irq
                       handle_pmi_common
   TEST PASSES ->        test_bit(bit, cpuc->active_mask))
                           perf_event_overflow
                             perf_prepare_sample
                             {
                               ...
                               if (!(sample_type & __PERF_SAMPLE_CALLCHAIN_EARLY))
                                     data->callchain = perf_callchain(event, regs);

         CRASH ->              size += data->callchain->nr;
                             }
                   </NMI>
              ...
              x86_pmu_disable_event(event)
            }

            __clear_bit(hwc->idx, cpuc->active_mask);

Fixing this by disabling the event itself before setting
off the PEBS bit.

Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: David Arcari <darcari@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Lendacky Thomas <Thomas.Lendacky@amd.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Fixes: 3966c3feca3f ("x86/perf/amd: Remove need to check "running" bit in NMI handler")
Link: http://lkml.kernel.org/r/20190504151556.31031-1-jolsa@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
5 years agoMerge tag 'powerpc-5.1-7' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Linus Torvalds [Sat, 4 May 2019 19:24:05 +0000 (12:24 -0700)]
Merge tag 'powerpc-5.1-7' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc fix from Michael Ellerman:
 "One regression fix.

  Changes we merged to STRICT_KERNEL_RWX on 32-bit were causing crashes
  under load on some machines depending on memory layout.

  Thanks to Christophe Leroy"

* tag 'powerpc-5.1-7' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  powerpc/32s: Fix BATs setting with CONFIG_STRICT_KERNEL_RWX

5 years agoblock: don't drain in-progress dispatch in blk_cleanup_queue()
Ming Lei [Tue, 30 Apr 2019 01:52:29 +0000 (09:52 +0800)]
block: don't drain in-progress dispatch in blk_cleanup_queue()

Now freeing hw queue resource is moved to hctx's release handler,
we don't need to worry about the race between blk_cleanup_queue and
run queue any more.

So don't drain in-progress dispatch in blk_cleanup_queue().

This is basically revert of c2856ae2f315 ("blk-mq: quiesce queue before
freeing queue").

Cc: Dongli Zhang <dongli.zhang@oracle.com>
Cc: James Smart <james.smart@broadcom.com>
Cc: Bart Van Assche <bart.vanassche@wdc.com>
Cc: linux-scsi@vger.kernel.org,
Cc: Martin K . Petersen <martin.petersen@oracle.com>,
Cc: Christoph Hellwig <hch@lst.de>,
Cc: James E . J . Bottomley <jejb@linux.vnet.ibm.com>,
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Tested-by: James Smart <james.smart@broadcom.com>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
5 years agoblk-mq: move cancel of hctx->run_work into blk_mq_hw_sysfs_release
Ming Lei [Tue, 30 Apr 2019 01:52:28 +0000 (09:52 +0800)]
blk-mq: move cancel of hctx->run_work into blk_mq_hw_sysfs_release

hctx is always released after requeue is freed.

With holding queue's kobject refcount, it is safe for driver to run queue,
so one run queue might be scheduled after blk_sync_queue() is done.

So moving the cancel of hctx->run_work into blk_mq_hw_sysfs_release()
for avoiding run released queue.

Cc: Dongli Zhang <dongli.zhang@oracle.com>
Cc: James Smart <james.smart@broadcom.com>
Cc: Bart Van Assche <bart.vanassche@wdc.com>
Cc: linux-scsi@vger.kernel.org,
Cc: Martin K . Petersen <martin.petersen@oracle.com>,
Cc: Christoph Hellwig <hch@lst.de>,
Cc: James E . J . Bottomley <jejb@linux.vnet.ibm.com>,
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Tested-by: James Smart <james.smart@broadcom.com>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
5 years agoblk-mq: always free hctx after request queue is freed
Ming Lei [Tue, 30 Apr 2019 01:52:27 +0000 (09:52 +0800)]
blk-mq: always free hctx after request queue is freed

In normal queue cleanup path, hctx is released after request queue
is freed, see blk_mq_release().

However, in __blk_mq_update_nr_hw_queues(), hctx may be freed because
of hw queues shrinking. This way is easy to cause use-after-free,
because: one implicit rule is that it is safe to call almost all block
layer APIs if the request queue is alive; and one hctx may be retrieved
by one API, then the hctx can be freed by blk_mq_update_nr_hw_queues();
finally use-after-free is triggered.

Fixes this issue by always freeing hctx after releasing request queue.
If some hctxs are removed in blk_mq_update_nr_hw_queues(), introduce
a per-queue list to hold them, then try to resuse these hctxs if numa
node is matched.

Cc: Dongli Zhang <dongli.zhang@oracle.com>
Cc: James Smart <james.smart@broadcom.com>
Cc: Bart Van Assche <bart.vanassche@wdc.com>
Cc: linux-scsi@vger.kernel.org,
Cc: Martin K . Petersen <martin.petersen@oracle.com>,
Cc: Christoph Hellwig <hch@lst.de>,
Cc: James E . J . Bottomley <jejb@linux.vnet.ibm.com>,
Reviewed-by: Hannes Reinecke <hare@suse.com>
Tested-by: James Smart <james.smart@broadcom.com>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
5 years agoblk-mq: split blk_mq_alloc_and_init_hctx into two parts
Ming Lei [Tue, 30 Apr 2019 01:52:26 +0000 (09:52 +0800)]
blk-mq: split blk_mq_alloc_and_init_hctx into two parts

Split blk_mq_alloc_and_init_hctx into two parts, and one is
blk_mq_alloc_hctx() for allocating all hctx resources, another
is blk_mq_init_hctx() for initializing hctx, which serves as
counter-part of blk_mq_exit_hctx().

Cc: Dongli Zhang <dongli.zhang@oracle.com>
Cc: James Smart <james.smart@broadcom.com>
Cc: Bart Van Assche <bart.vanassche@wdc.com>
Cc: linux-scsi@vger.kernel.org
Cc: Martin K . Petersen <martin.petersen@oracle.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: James E . J . Bottomley <jejb@linux.vnet.ibm.com>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Tested-by: James Smart <james.smart@broadcom.com>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
5 years agoblk-mq: free hw queue's resource in hctx's release handler
Ming Lei [Tue, 30 Apr 2019 01:52:25 +0000 (09:52 +0800)]
blk-mq: free hw queue's resource in hctx's release handler

Once blk_cleanup_queue() returns, tags shouldn't be used any more,
because blk_mq_free_tag_set() may be called. Commit 45a9c9d909b2
("blk-mq: Fix a use-after-free") fixes this issue exactly.

However, that commit introduces another issue. Before 45a9c9d909b2,
we are allowed to run queue during cleaning up queue if the queue's
kobj refcount is held. After that commit, queue can't be run during
queue cleaning up, otherwise oops can be triggered easily because
some fields of hctx are freed by blk_mq_free_queue() in blk_cleanup_queue().

We have invented ways for addressing this kind of issue before, such as:

8dc765d438f1 ("SCSI: fix queue cleanup race before queue initialization is done")
c2856ae2f315 ("blk-mq: quiesce queue before freeing queue")

But still can't cover all cases, recently James reports another such
kind of issue:

https://marc.info/?l=linux-scsi&m=155389088124782&w=2

This issue can be quite hard to address by previous way, given
scsi_run_queue() may run requeues for other LUNs.

Fixes the above issue by freeing hctx's resources in its release handler, and this
way is safe becasue tags isn't needed for freeing such hctx resource.

This approach follows typical design pattern wrt. kobject's release handler.

Cc: Dongli Zhang <dongli.zhang@oracle.com>
Cc: James Smart <james.smart@broadcom.com>
Cc: Bart Van Assche <bart.vanassche@wdc.com>
Cc: linux-scsi@vger.kernel.org,
Cc: Martin K . Petersen <martin.petersen@oracle.com>,
Cc: Christoph Hellwig <hch@lst.de>,
Cc: James E . J . Bottomley <jejb@linux.vnet.ibm.com>,
Reported-by: James Smart <james.smart@broadcom.com>
Fixes: 45a9c9d909b2 ("blk-mq: Fix a use-after-free")
Cc: stable@vger.kernel.org
Reviewed-by: Hannes Reinecke <hare@suse.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Tested-by: James Smart <james.smart@broadcom.com>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
5 years agoblk-mq: move cancel of requeue_work into blk_mq_release
Ming Lei [Tue, 30 Apr 2019 01:52:24 +0000 (09:52 +0800)]
blk-mq: move cancel of requeue_work into blk_mq_release

With holding queue's kobject refcount, it is safe for driver
to schedule requeue. However, blk_mq_kick_requeue_list() may
be called after blk_sync_queue() is done because of concurrent
requeue activities, then requeue work may not be completed when
freeing queue, and kernel oops is triggered.

So moving the cancel of requeue_work into blk_mq_release() for
avoiding race between requeue and freeing queue.

Cc: Dongli Zhang <dongli.zhang@oracle.com>
Cc: James Smart <james.smart@broadcom.com>
Cc: Bart Van Assche <bart.vanassche@wdc.com>
Cc: linux-scsi@vger.kernel.org,
Cc: Martin K . Petersen <martin.petersen@oracle.com>,
Cc: Christoph Hellwig <hch@lst.de>,
Cc: James E . J . Bottomley <jejb@linux.vnet.ibm.com>,
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Tested-by: James Smart <james.smart@broadcom.com>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
5 years agoblk-mq: grab .q_usage_counter when queuing request from plug code path
Ming Lei [Tue, 30 Apr 2019 01:52:23 +0000 (09:52 +0800)]
blk-mq: grab .q_usage_counter when queuing request from plug code path

Just like aio/io_uring, we need to grab 2 refcount for queuing one
request, one is for submission, another is for completion.

If the request isn't queued from plug code path, the refcount grabbed
in generic_make_request() serves for submission. In theroy, this
refcount should have been released after the sumission(async run queue)
is done. blk_freeze_queue() works with blk_sync_queue() together
for avoiding race between cleanup queue and IO submission, given async
run queue activities are canceled because hctx->run_work is scheduled with
the refcount held, so it is fine to not hold the refcount when
running the run queue work function for dispatch IO.

However, if request is staggered into plug list, and finally queued
from plug code path, the refcount in submission side is actually missed.
And we may start to run queue after queue is removed because the queue's
kobject refcount isn't guaranteed to be grabbed in flushing plug list
context, then kernel oops is triggered, see the following race:

blk_mq_flush_plug_list():
        blk_mq_sched_insert_requests()
                insert requests to sw queue or scheduler queue
                blk_mq_run_hw_queue

Because of concurrent run queue, all requests inserted above may be
completed before calling the above blk_mq_run_hw_queue. Then queue can
be freed during the above blk_mq_run_hw_queue().

Fixes the issue by grab .q_usage_counter before calling
blk_mq_sched_insert_requests() in blk_mq_flush_plug_list(). This way is
safe because the queue is absolutely alive before inserting request.

Cc: Dongli Zhang <dongli.zhang@oracle.com>
Cc: James Smart <james.smart@broadcom.com>
Cc: linux-scsi@vger.kernel.org,
Cc: Martin K . Petersen <martin.petersen@oracle.com>,
Cc: Christoph Hellwig <hch@lst.de>,
Cc: James E . J . Bottomley <jejb@linux.vnet.ibm.com>,
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Tested-by: James Smart <james.smart@broadcom.com>
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
5 years agoMerge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Linus Torvalds [Fri, 3 May 2019 23:49:46 +0000 (16:49 -0700)]
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM fixes from Paolo Bonzini:

 - PPC and ARM bugfixes from submaintainers

 - Fix old Windows versions on AMD (recent regression)

 - Fix old Linux versions on processors without EPT

 - Fixes for LAPIC timer optimizations

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (21 commits)
  KVM: nVMX: Fix size checks in vmx_set_nested_state
  KVM: selftests: make hyperv_cpuid test pass on AMD
  KVM: lapic: Check for in-kernel LAPIC before deferencing apic pointer
  KVM: fix KVM_CLEAR_DIRTY_LOG for memory slots of unaligned size
  x86/kvm/mmu: reset MMU context when 32-bit guest switches PAE
  KVM: x86: Whitelist port 0x7e for pre-incrementing %rip
  Documentation: kvm: fix dirty log ioctl arch lists
  KVM: VMX: Move RSB stuffing to before the first RET after VM-Exit
  KVM: arm/arm64: Don't emulate virtual timers on userspace ioctls
  kvm: arm: Skip stage2 huge mappings for unaligned ipa backed by THP
  KVM: arm/arm64: Ensure vcpu target is unset on reset failure
  KVM: lapic: Convert guest TSC to host time domain if necessary
  KVM: lapic: Allow user to disable adaptive tuning of timer advancement
  KVM: lapic: Track lapic timer advance per vCPU
  KVM: lapic: Disable timer advancement if adaptive tuning goes haywire
  x86: kvm: hyper-v: deal with buggy TLB flush requests from WS2012
  KVM: x86: Consider LAPIC TSC-Deadline timer expired if deadline too short
  KVM: PPC: Book3S: Protect memslots while validating user address
  KVM: PPC: Book3S HV: Perserve PSSCR FAKE_SUSPEND bit on guest exit
  KVM: arm/arm64: vgic-v3: Retire pending interrupts on disabling LPIs
  ...

5 years agoparisc: Update huge TLB page support to use per-pagetable spinlock
John David Anglin [Sat, 27 Apr 2019 18:15:38 +0000 (14:15 -0400)]
parisc: Update huge TLB page support to use per-pagetable spinlock

This patch updates the parisc huge TLB page support to use per-pagetable spinlocks.

This patch requires Mikulas' per-pagetable spinlock patch and the revised TLB
serialization patch from Helge and myself.  With Mikulas' patch, we need to use
the per-pagetable spinlock for page table updates.  The TLB lock is only used
to serialize TLB flushes on machines with the Merced bus.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Use per-pagetable spinlock
Mikulas Patocka [Sat, 27 Apr 2019 22:09:53 +0000 (00:09 +0200)]
parisc: Use per-pagetable spinlock

PA-RISC uses a global spinlock to protect pagetable updates in the TLB
fault handlers. When multiple cores are taking TLB faults simultaneously,
the cache line containing the spinlock becomes a bottleneck.

This patch embeds the spinlock in the top level page directory, so that
every process has its own lock. It improves performance by 30% when
doing parallel compilations.

At least on the N class systems, only one PxTLB inter processor
broadcast can be active at any one time on the Merced bus. If a Merced
bus is found, this patch serializes the TLB flushes with the
pa_tlb_flush_lock spinlock.

v1: Initial patch by Mikulas
v2: Added Merced detection by Helge
v3: Revised TLB serialization by Dave & Helge

Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: John David Anglin <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Allow live-patching of __meminit functions
Helge Deller [Wed, 1 May 2019 12:59:58 +0000 (14:59 +0200)]
parisc: Allow live-patching of __meminit functions

When making the text sections writeable with set_kernel_text_rw(1),
include all text sections including those in the __init section.
Otherwise functions marked with __meminit will stay read-only.

Signed-off-by: Helge Deller <deller@gmx.de>
Cc: <stable@vger.kernel.org> # 4.20+
5 years agoparisc: Add memory barrier to asm pdc and sync instructions
Helge Deller [Sat, 27 Apr 2019 21:57:49 +0000 (23:57 +0200)]
parisc: Add memory barrier to asm pdc and sync instructions

Add compiler memory barriers to ensure the compiler doesn't reorder memory
operations around these instructions.

Cc: stable@vger.kernel.org # v4.20+
Fixes: 3847dab77421 ("parisc: Add alternative coding infrastructure")
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Add memory clobber to TLB purges
John David Anglin [Sun, 21 Apr 2019 23:47:17 +0000 (19:47 -0400)]
parisc: Add memory clobber to TLB purges

The pdtlb and pitlb instructions are strongly ordered. The asms invoking
these instructions should be compiler memory barriers to ensure the
compiler doesn't reorder memory operations around these instructions.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
CC: stable@vger.kernel.org # v4.20+
Fixes: 3847dab77421 ("parisc: Add alternative coding infrastructure")
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Use ldcw instruction for SMP spinlock release barrier
John David Anglin [Sun, 14 Apr 2019 23:20:40 +0000 (19:20 -0400)]
parisc: Use ldcw instruction for SMP spinlock release barrier

There are only a couple of instructions that can function as a memory
barrier on parisc.  Currently, we use the sync instruction as a memory
barrier when releasing a spinlock.  However, the ldcw instruction is a
better barrier when we have a handy memory location since it operates in
the cache on coherent machines.

This patch updates the spinlock release code to use ldcw.  I also
changed the "stw,ma" instructions to "stw" instructions as it is not an
adequate barrier.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Remove lock code to serialize TLB operations in pacache.S
John David Anglin [Fri, 12 Apr 2019 23:12:04 +0000 (19:12 -0400)]
parisc: Remove lock code to serialize TLB operations in pacache.S

TLB operations only need to be serialized on machines with the Merced
(Stretch) bus. The only machines in this category are L and N class, and
they require a 64-bit PA 2.0 kernel. On these machines, we use local TLB
purges in the tmpalias routines.
We don't need to serialize TLB purges on all other machines. Thus, the
lock/unlock code can be removed when CONFIG_PA20 is not defined.
Further, when CONFIG_PA20 is not defined, alternative patching converts
the TLB purges to local purges when PA 2.0 hardware has been detected.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Tested-By: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Switch from DISCONTIGMEM to SPARSEMEM
Helge Deller [Tue, 9 Apr 2019 19:52:35 +0000 (21:52 +0200)]
parisc: Switch from DISCONTIGMEM to SPARSEMEM

The commit 1c30844d2dfe ("mm: reclaim small amounts of memory when an
external fragmentation event occurs") breaks memory management on a
parisc c8000 workstation with this memory layout:

0) Start 0x0000000000000000 End 0x000000003fffffff Size   1024 MB
1) Start 0x0000000100000000 End 0x00000001bfdfffff Size   3070 MB
2) Start 0x0000004040000000 End 0x00000040ffffffff Size   3072 MB

With the patch 1c30844d2dfe, the kernel will incorrectly reclaim the
first zone when it fills up, ignoring the fact that there are two
completely free zones. Basiscally, it limits cache size to 1GiB.

The parisc kernel is currently using the DISCONTIGMEM implementation,
but isn't NUMA. Avoid this issue or strange work-arounds by switching to
the more commonly used SPARSEMEM implementation.

Reported-by: Mikulas Patocka <mpatocka@redhat.com>
Fixes: 1c30844d2dfe ("mm: reclaim small amounts of memory when an external fragmentation event occurs")
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: enable wide mode early
Sven Schnelle [Thu, 18 Apr 2019 09:33:13 +0000 (11:33 +0200)]
parisc: enable wide mode early

The idle task might have been allocated above 4GB. With the current code
we cannot access that memory because the CPU is still running in narrow
mode.
This was found on a J5000 machine and the patch is required to enable
SPARSEMEM on that machine.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: update feature lists
Sven Schnelle [Tue, 9 Apr 2019 20:05:24 +0000 (22:05 +0200)]
parisc: update feature lists

Update lists to reflect that we have now KGDB and kretprobes
support.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Show n/a if product number not available
Helge Deller [Tue, 9 Apr 2019 20:22:29 +0000 (22:22 +0200)]
parisc: Show n/a if product number not available

Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: remove unused flags parameter in __patch_text()
Sven Schnelle [Tue, 9 Apr 2019 17:30:30 +0000 (19:30 +0200)]
parisc: remove unused flags parameter in __patch_text()

It's not used by patch_map()/patch_unmap(), so lets remove
it.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agodoc: update kprobes supported architecture list
Sven Schnelle [Tue, 9 Apr 2019 17:30:29 +0000 (19:30 +0200)]
doc: update kprobes supported architecture list

Now that kprobes and kretprobes are implemented, update the list in
Documentation to reflect that.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Implement kretprobes
Sven Schnelle [Tue, 9 Apr 2019 17:30:28 +0000 (19:30 +0200)]
parisc: Implement kretprobes

Implement kretprobes on parisc, parts stolen from powerpc.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: remove kprobes.h from generic-y
Sven Schnelle [Tue, 9 Apr 2019 17:30:27 +0000 (19:30 +0200)]
parisc: remove kprobes.h from generic-y

We're providing our own version now.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Implement kprobes
Sven Schnelle [Sun, 7 Apr 2019 18:10:58 +0000 (20:10 +0200)]
parisc: Implement kprobes

Implement kprobes support for PA-RISC.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: add functions required by KPROBE_EVENTS
Sven Schnelle [Sun, 7 Apr 2019 18:10:57 +0000 (20:10 +0200)]
parisc: add functions required by KPROBE_EVENTS

implement regs_get_register(), regs_get_kernel_stack_nth() and
regs_within_kernel_stack()

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: PA-Linux requires at least 32 MB RAM
Helge Deller [Sat, 6 Apr 2019 23:09:23 +0000 (01:09 +0200)]
parisc: PA-Linux requires at least 32 MB RAM

Even a 32-bit kernel requires at least 27 MB to decompress itself, so
halt the system with a message if the system has less memory than 32 MB.

Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Skip registering LED when running in QEMU
Helge Deller [Tue, 2 Apr 2019 10:17:08 +0000 (12:17 +0200)]
parisc: Skip registering LED when running in QEMU

No need to spend CPU cycles when we run on QEMU.

Signed-off-by: Helge Deller <deller@gmx.de>
CC: stable@vger.kernel.org # v4.9+
5 years agoparisc: Tune LASI LAN for QEMU
Helge Deller [Tue, 2 Apr 2019 10:21:13 +0000 (12:21 +0200)]
parisc: Tune LASI LAN for QEMU

Do not loose cycles when we run on QEMU, and fix one trivial typo.

Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Export running_on_qemu symbol for modules
Helge Deller [Sat, 6 Apr 2019 14:45:14 +0000 (16:45 +0200)]
parisc: Export running_on_qemu symbol for modules

Signed-off-by: Helge Deller <deller@gmx.de>
CC: stable@vger.kernel.org # v4.9+
5 years agoparisc: add KGDB support
Sven Schnelle [Thu, 4 Apr 2019 19:14:10 +0000 (21:14 +0200)]
parisc: add KGDB support

This patch add KGDB support to PA-RISC. It also implements
single-stepping utilizing the recovery counter.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: add parisc code patching
Sven Schnelle [Thu, 4 Apr 2019 19:14:09 +0000 (21:14 +0200)]
parisc: add parisc code patching

Instead of re-mapping the whole kernel text with RWX rights
add a patch_text() which can be used to replace instructions
in the kernel .text section. Based on the ARM implementation.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: add set_fixmap()/clear_fixmap()
Sven Schnelle [Thu, 4 Apr 2019 19:14:08 +0000 (21:14 +0200)]
parisc: add set_fixmap()/clear_fixmap()

These functions will be used for adding code patching
functions later.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agoparisc: Consider stack randomization for mmap base only when necessary
Alexandre Ghiti [Thu, 4 Apr 2019 06:26:22 +0000 (02:26 -0400)]
parisc: Consider stack randomization for mmap base only when necessary

Do not offset mmap base address because of stack randomization if
current task does not want randomization.

Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
Signed-off-by: Helge Deller <deller@gmx.de>
5 years agohwmon: (lm75) Add support for TMP75B
Iker Perez del Palomar Sustatxa [Fri, 3 May 2019 16:15:00 +0000 (17:15 +0100)]
hwmon: (lm75) Add support for TMP75B

The TMP75B has a different control register, supports 12-bit
resolution and the default conversion rate is 37 Hz.

Signed-off-by: Iker Perez del Palomar Sustatxa <iker.perez@codethink.co.uk>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
5 years agodt-bindings: hwmon: Add tmp75b to lm75.txt
Iker Perez del Palomar Sustatxa [Fri, 3 May 2019 16:15:01 +0000 (17:15 +0100)]
dt-bindings: hwmon: Add tmp75b to lm75.txt

Update the LM75's devicetree definition to allow Texas Instruments
TMP75B be probed.

Signed-off-by: Iker Perez del Palomar Sustatxa <iker.perez@codethink.co.uk>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
5 years agolivepatch: Remove duplicated code for early initialization
Petr Mladek [Fri, 3 May 2019 13:26:25 +0000 (15:26 +0200)]
livepatch: Remove duplicated code for early initialization

kobject_init() call added one more operation that has to be
done when doing the early initialization of both static and
dynamic livepatch structures.

It would have been easier when the early initialization code
was not duplicated. Let's deduplicate it for future generations
of livepatching hackers.

The patch does not change the existing behavior.

Signed-off-by: Petr Mladek <pmladek@suse.com>
Reviewed-by: Kamalesh Babulal <kamalesh@linux.vnet.ibm.com>
Acked-by: Joe Lawrence <joe.lawrence@redhat.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
5 years agolivepatch: Remove custom kobject state handling
Petr Mladek [Fri, 3 May 2019 13:26:24 +0000 (15:26 +0200)]
livepatch: Remove custom kobject state handling

kobject_init() always succeeds and sets the reference count to 1.
It allows to always free the structures via kobject_put() and
the related release callback.

Note that the custom kobject state handling was used only
because we did not know that kobject_put() can and actually
should get called even when kobject_init_and_add() fails.

The patch should not change the existing behavior.

Suggested-by: "Tobin C. Harding" <tobin@kernel.org>
Signed-off-by: Petr Mladek <pmladek@suse.com>
Reviewed-by: Kamalesh Babulal <kamalesh@linux.vnet.ibm.com>
Acked-by: Joe Lawrence <joe.lawrence@redhat.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
5 years agoMerge branch 'i2c/for-current-fixed' of ssh://gitolite.kernel.org/pub/scm/linux/kerne...
Linus Torvalds [Fri, 3 May 2019 18:42:01 +0000 (11:42 -0700)]
Merge branch 'i2c/for-current-fixed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull i2c fixes from Wolfram Sang:
 "I2C driver bugfixes and a MAINTAINERS update for you"

* 'i2c/for-current-fixed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  i2c: Prevent runtime suspend of adapter when Host Notify is required
  i2c: synquacer: fix enumeration of slave devices
  MAINTAINERS: friendly takeover of i2c-gpio driver
  i2c: designware: ratelimit 'transfer when suspended' errors
  i2c: imx: correct the method of getting private data in notifier_call

5 years agonohz_full: Allow the boot CPU to be nohz_full
Nicholas Piggin [Thu, 11 Apr 2019 03:34:48 +0000 (13:34 +1000)]
nohz_full: Allow the boot CPU to be nohz_full

Allow the boot CPU/CPU0 to be nohz_full. Have the boot CPU take the
do_timer duty during boot until a housekeeping CPU can take over.

This is supported when CONFIG_PM_SLEEP_SMP is not configured, or when
it is configured and the arch allows suspend on non-zero CPUs.

nohz_full has been trialed at a large supercomputer site and found to
significantly reduce jitter. In order to deploy it in production, they
need CPU0 to be nohz_full because their job control system requires
the application CPUs to start from 0, and the housekeeping CPUs are
placed higher. An equivalent job scheduling that uses CPU0 for
housekeeping could be achieved by modifying their system, but it is
preferable if nohz_full can support their environment without
modification.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lkml.kernel.org/r/20190411033448.20842-6-npiggin@gmail.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
5 years agosched/isolation: Require a present CPU in housekeeping mask
Nicholas Piggin [Thu, 11 Apr 2019 03:34:47 +0000 (13:34 +1000)]
sched/isolation: Require a present CPU in housekeeping mask

During housekeeping mask setup, currently a possible CPU is required.
That does not guarantee the CPU would be available at boot time, so
check to ensure that at least one present CPU is in the mask.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lkml.kernel.org/r/20190411033448.20842-5-npiggin@gmail.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
5 years agokernel/cpu: Allow non-zero CPU to be primary for suspend / kexec freeze
Nicholas Piggin [Thu, 11 Apr 2019 03:34:46 +0000 (13:34 +1000)]
kernel/cpu: Allow non-zero CPU to be primary for suspend / kexec freeze

This patch provides an arch option, ARCH_SUSPEND_NONZERO_CPU, to
opt-in to allowing suspend to occur on one of the housekeeping CPUs
rather than hardcoded CPU0.

This will allow CPU0 to be a nohz_full CPU with a later change.

It may be possible for platforms with hardware/firmware restrictions
on suspend/wake effectively support this by handing off the final
stage to CPU0 when kernel housekeeping is no longer required. Another
option is to make housekeeping / nohz_full mask dynamic at runtime,
but the complexity could not be justified at this time.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lkml.kernel.org/r/20190411033448.20842-4-npiggin@gmail.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
5 years agopower/suspend: Add function to disable secondaries for suspend
Nicholas Piggin [Thu, 11 Apr 2019 03:34:45 +0000 (13:34 +1000)]
power/suspend: Add function to disable secondaries for suspend

This adds a function to disable secondary CPUs for suspend that are
not necessarily non-zero / non-boot CPUs. Platforms will be able to
use this to suspend using non-zero CPUs.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lkml.kernel.org/r/20190411033448.20842-3-npiggin@gmail.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
5 years agointel_th: msu: Add current window tracking
Alexander Shishkin [Fri, 3 May 2019 08:44:51 +0000 (11:44 +0300)]
intel_th: msu: Add current window tracking

Now that we have a way to switch between MSC buffer windows, add code to
track the current window. The hardware register NWSA that contains the
address of the next window is unfortunately not always usable, and since
the driver has full control of the window switching, there is no reason
not to keep this on the software side.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5 years agointel_th: msu: Add a sysfs attribute to trigger window switch
Alexander Shishkin [Fri, 3 May 2019 08:44:50 +0000 (11:44 +0300)]
intel_th: msu: Add a sysfs attribute to trigger window switch

Now that we have the means to trigger a window switch for the MSU trace
store, add a sysfs file to allow triggering it from userspace.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5 years agointel_th: msu: Correct the block wrap detection
Alexander Shishkin [Fri, 3 May 2019 08:44:49 +0000 (11:44 +0300)]
intel_th: msu: Correct the block wrap detection

In multi window mode the MSU will set "window wrap" bit to indicate block
wrapping as well. Take this into account when checking data blocks.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5 years agointel_th: Add switch triggering support
Alexander Shishkin [Fri, 3 May 2019 08:44:48 +0000 (11:44 +0300)]
intel_th: Add switch triggering support

Add support for asserting window switch trigger when tracing to MSU output
ports. This allows for software controlled switching between windows of
the MSU buffer, which can be used for double buffering while exporting the
trace data further from the MSU.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5 years agointel_th: gth: Factor out trace start/stop
Alexander Shishkin [Fri, 3 May 2019 08:44:47 +0000 (11:44 +0300)]
intel_th: gth: Factor out trace start/stop

The trace enable/disable functions of the GTH include the code that starts
and stops trace flom from the sources. This start/stop functionality will
also be used in the window switch trigger sequence.

Factor out start/stop code from the larger trace enable/disable code in
preparation for the window switch sequence.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5 years agointel_th: msu: Factor out pipeline draining
Alexander Shishkin [Fri, 3 May 2019 08:44:46 +0000 (11:44 +0300)]
intel_th: msu: Factor out pipeline draining

The code that waits for the pipeline empty condition of the MSU is
currently called in the path that disables the trace. We will also
need this in the window switch trigger sequence. Therefore, factor
out this code and make it accessible to the GTH device.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5 years agointel_th: msu: Switch over to scatterlist
Alexander Shishkin [Fri, 3 May 2019 08:44:44 +0000 (11:44 +0300)]
intel_th: msu: Switch over to scatterlist

Instead of using a home-grown array of pointers to the DMA pages, switch
over to scatterlist data types and accessors, which has all the convenient
accessors, can be used to batch-map DMA memory and is convenient for
passing around between different layers, which will be useful when MSU
buffer management has to cross the boundaries of the MSU driver.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5 years agointel_th: msu: Replace open-coded list_{first,last,next}_entry variants
Alexander Shishkin [Fri, 3 May 2019 08:44:43 +0000 (11:44 +0300)]
intel_th: msu: Replace open-coded list_{first,last,next}_entry variants

There are a few places in the code where open-coded versions of list entry
accessors list_first_entry()/list_last_entry()/list_next_entry() are used.

Replace those with the standard macros.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5 years agointel_th: Only report useful IRQs to subdevices
Alexander Shishkin [Fri, 3 May 2019 08:44:42 +0000 (11:44 +0300)]
intel_th: Only report useful IRQs to subdevices

The only type of IRQ triggering event that is useful to us at the moment
is the "last block" interrupt of the MSU. This interrupt can only be
enabled via "MINTCTL" register that doesn't exist in earlier version of
the Intel TH.

Enumerate the presence of MINTCTL via per-device driver data structure
and only instantiate the IRQ resource for subdevices if this capability
is present.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5 years agointel_th: msu: Start handling IRQs
Alexander Shishkin [Fri, 3 May 2019 08:44:41 +0000 (11:44 +0300)]
intel_th: msu: Start handling IRQs

We intend to use the interrupt to detect Last Block condition in the MSU
driver, which we can use for double-buffering software-managed data
transfers.

Add an interrupt handler to the MSU driver.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5 years agointel_th: pci: Use MSI interrupt signalling
Alexander Shishkin [Fri, 3 May 2019 08:44:40 +0000 (11:44 +0300)]
intel_th: pci: Use MSI interrupt signalling

Since Intel TH is capable of MSI interrupt signalling, make use of it.
The way it works is, each of the 7 interrupt triggering events has its
own vector in this mode, as opposed to interrupt line delivery, where
all events are signalled via the same line. Failing to enable MSI, the
driver falls back to using an interrupt line.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>