Arvind Yadav [Mon, 28 Aug 2017 07:02:41 +0000 (12:32 +0530)]
clk: ux500: prcc: constify clk_ops.
clk_ops are not supposed to change at runtime. All functions
working with clk_ops provided by <linux/clk-provider.h> work
with const clk_ops. So mark the non-const clk_ops as const.
Here, Function "clk_reg_prcc" is used to initialized clk_init_data.
clk_init_data is working with const clk_ops. So make clk_reg_prcc
non-const clk_ops argument as const.
Arvind Yadav [Mon, 28 Aug 2017 07:02:40 +0000 (12:32 +0530)]
clk: ux500: sysctrl: constify clk_ops.
clk_ops are not supposed to change at runtime. All functions
working with clk_ops provided by <linux/clk-provider.h> work
with const clk_ops. So mark the non-const clk_ops as const.
Here, Function "clk_reg_sysctrl" is used to initialized clk_init_data.
clk_init_data is working with const clk_ops. So make clk_reg_sysctrl
non-const clk_ops argument as const.
Arvind Yadav [Mon, 28 Aug 2017 07:02:39 +0000 (12:32 +0530)]
clk: ux500: prcmu: constify clk_ops.
clk_ops are not supposed to change at runtime. All functions
working with clk_ops provided by <linux/clk-provider.h> work
with const clk_ops. So mark the non-const clk_ops as const.
Here, Function "clk_reg_prcmu" is used to initialized clk_init_data.
clk_init_data is working with const clk_ops. So make clk_reg_prcmu
non-const clk_ops argument as const.
Alex Frid [Tue, 25 Jul 2017 10:34:15 +0000 (13:34 +0300)]
clk: tegra: Fix Tegra210 PLLU initialization
- Added necessary delays in PLLU enable sequence during initialization
- Applied PLLU lock to all secondary gates (PLLU_48M and PLLU_60M were
missing).
Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Increased Tegra210 UTMIPLL power on delay to 20us (spec maximum is 15us).
Also remove a few empty lines to make it more clear the ACTIVE_DLY_COUNT
and ENABLE_DLY_COUNT fields.
Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Alex Frid [Tue, 25 Jul 2017 10:34:13 +0000 (13:34 +0300)]
clk: tegra: Fix T210 PLLRE registration
Switched Tegra210 PLLRE registration to common PLL ops instead of special
PLLRE ops used on previous Tegra chips. The latter ops do not follow
chip specific PLL frequency table, and do not apply chip specific rate
calculation method.
Removed unnecessary default rate setting that duplicates h/w reset
state, and is overwritten by clock initialization, anyway.
Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Remove from Tegra210 PLLSS registration code sections that
- attempt to set PLL minimum rate (unnecessary, and dangerous if PLL
is already enabled on boot)
- apply pre-Tegra210 defaults settings
- check IDDQ setting (duplicated with Tegra210 PLLSS check defaults)
Replaced setting of reference clock with check that default oscillator
selection is not changed, and failed registration otherwise as validation
was only done with the oscillator as the reference clock.
Reordered registration, so that PLL initialization is called after
VCOmin adjustment.
Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Alex Frid [Tue, 25 Jul 2017 10:34:11 +0000 (13:34 +0300)]
clk: tegra: Re-factor T210 PLLX registration
Tegra210 PLLX uses the same sequences than then PLLC instances. So there
is no need to have a special registration function and ops struct for it.
Simplify the code by changing all references to the Tegra210 PLLX
registration function to the Tegra210 PLLC registration function and
avoid duplicate functionality.
Based on work by Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Not all fields are read from the hw depending on the PLL type. Make sure
the other fields are 0 by clearing the structure beforehand to prevent
users such as the rate re-calculation code from using bogus values.
Based on work by Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
PLL SS was only controlled when setting the PLL rate, not when the PLL itself
is enabled or disabled.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Georgi Djakov [Fri, 18 Aug 2017 14:22:50 +0000 (17:22 +0300)]
clk: qcom: msm8916: Fix bimc gpu clock ops
The clock bimc_gpu_clk_src is incorrectly set to use the shared rcg2
ops, which are for RCGs with child branches controlled by different
CPUs.
The result of the incorrect ops is that the GPU's PM runtime may leave
this clock set at a very low rate. Fix this issue by using the correct
rcg2 ops.
Fixes: a2e8272f3f89 ("clk: qcom: Add MSM8916 gpu clocks") Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Wed, 23 Aug 2017 22:39:58 +0000 (15:39 -0700)]
Merge tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
* Add more module clocks for R-Car V2H and M3-W,
* Add support for the R-Car Gen3 USB 2.0 clock selector PHY,
* Add support for the new R-Car D3 SoC,
* Allow compile-testing of all (sub)drivers now all dummy infrastructure
is available,
* Small fixes and cleanups.
* tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a7796: Add USB3.0 clock
clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY
clk: renesas: cpg-mssr: Add R8A77995 support
clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
clk: renesas: Add r8a77995 CPG Core Clock Definitions
clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table
clk: renesas: rcar-gen3-cpg: Drop superfluous variable
clk: renesas: Allow compile-testing of all (sub)drivers
clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks
clk: renesas: div6: Document fields used for parent selection
Stephen Boyd [Wed, 23 Aug 2017 22:33:45 +0000 (15:33 -0700)]
Merge tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull Rockchip clk driver updates from Heiko Stuebner:
The biggest change is fixing the jitter on the fractional clock-type
Rockchip socs experience with the default approximation. For that we
introduce the ability to override it with a clock-specific approximation
and use that to create the needed rate settings as described in the
Rockchip soc manuals (same for all Rockchip socs).
Apart from that we have support for the rk3126 clock controller
which is similar to the rk3128 with some minimal differences
and a lot of improvements and fixes for the rv1108 clock controller
(missing clocks, some clock-ids, naming fixes, register fixes).
* tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix the rv1108 clk_mac sel register description
clk: rockchip: rename rv1108 macphy clock to mac
clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocks
clk: rockchip: add rk3228 SCLK_SDIO_SRC clk id
clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID
clk: rockchip: add rk3228 sclk_sdio_src ID
clk: rockchip: add special approximation to fix up fractional clk's jitter
clk: fractional-divider: allow overriding of approximation
clk: rockchip: modify rk3128 clk driver to also support rk3126
dt-bindings: add documentation for rk3126 clock
clk: rockchip: add some critical clocks for rv1108 SoC
clk: rockchip: rename some of clks for rv1108 SoC
clk: rockchip: fix up some clks describe error for rv1108 SoC
clk: rockchip: support more clks for rv1108
clk: rockchip: fix up the pll clks error for rv1108 SoC
clk: rockchip: support more rates for rv1108 cpuclk
clk: rockchip: fix up indentation of some RV1108 clock-ids
clk: rockchip: rename the clk id for HCLK_I2S1_2CH
clk: rockchip: add more clk ids for rv1108
Stephen Boyd [Wed, 23 Aug 2017 22:31:48 +0000 (15:31 -0700)]
Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock changes from Chen-Yu Tsai:
* Added support for fixed post-divider on divider and NKM-style clocks
* Added driver for R40 CCU
* Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo
* Make fractional clock modes really used and correctly configured
* Make H3 cpu clock rate change correctly to be used with cpufreq
* tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: support R40 SoC
dt-bindings: add compatible string for Allwinner R40 CCU
clk: sunxi-ng: nkm: add support for fixed post-divider
clk: sunxi-ng: div: Add support for fixed post-divider
dt-bindings: clock: sunxi-ccu: Add compatibles for sun5i CCU driver
clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
clk: sunxi-ng: Wait for lock when using fractional mode
clk: sunxi-ng: Make fractional helper less chatty
clk: sunxi-ng: multiplier: Fix fractional mode
clk: sunxi-ng: Fix fractional mode for N-M clocks
clk: sunxi-ng: Fix header guard of ccu-sun8i-r.h
Stephen Boyd [Wed, 23 Aug 2017 22:30:29 +0000 (15:30 -0700)]
Merge tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next
Pull Samsung clk driver updates from Sylwester Nawrocki:
Changes in definitions of audio related clocks for Exynos5420/5422/5800
SoCs: a fix of mau_epll clock definition and changes enabling clock rate
setting propagation on a path from the I2S IP block up the EPLL.
* tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: exynos542x: Enable clock rate propagation up to the EPLL
clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks
clk: samsung: Fix mau_epll clock definition for exynos5422
Elaine Zhang [Mon, 21 Aug 2017 08:16:07 +0000 (16:16 +0800)]
clk: rockchip: fix the rv1108 clk_mac sel register description
The source clock ordering is wrong, as shown in the TRM:
cru_sel24_con[8]
rmii_extclk_sel
clock source select control register
1'b0: from internal PLL
1'b1: from external IO
clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY
R-Car USB 2.0 controller can change the clock source from an oscillator
to an external clock via a register. So, this patch adds support
the clock source selector as a clock driver.
Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 CPG code.
Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev.
0.55, Jun. 30, 2017.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org>
clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car
D3), a peripheral clock divider has been added, to select between clean
and spread spectrum parents.
Add a new clock type to the R-Car Gen3 driver core to handle this.
To avoid increasing the size of struct cpg_core_clk, both parents and
dividers are stored in the existing parent resp. div fields.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
value different from one. Extend struct rcar_gen3_cpg_pll_config to handle
this. As all multipliers and dividers are small, table size increase
can be kept limited by storing them in u8s instead of unsigned ints,
which saves ca. 0.5 KiB for a generic kernel.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Add all R-Car D3 Clock Pulse Generator Core Clock Outputs, as listed
in Table 8.2f ("List of Clocks [R-Car D3]") of the R-Car Series, 3rd
Generation Hardware User's Manual (Rev. 0.55, Jun. 30, 2017).
Note that internal CPG clocks (S0, S1, S2, S3, S1C, S3C, SDSRC, and
SSPSRC) are not included, as they are used as internal clock sources
only, and never referenced from DT.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
clk: samsung: exynos542x: Enable clock rate propagation up to the EPLL
The CLK_SET_RATE_PARENT flag is added to clocks between the EPLL
and the audio subsystem clock controller so that the EPLL's output
frequency can be set indirectly with clk_set_rate() on a leaf clock.
That should be safe as EPLL is normally only used to generate clock
for the audio subsystem.
With this change we can avoid passing the EPLL clock to the ASoC
machine driver.
clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks
This allows clk rate propagation up to the clock tree so EPLL
can be reprogrammed indirectly when setting rate of the Audio
Subsystem clocks.
The advantage is that sound machine driver can operate only
on the leaf clocks rather than explicitly re-configuring
the root clock (EPLL).
Elaine Zhang [Tue, 1 Aug 2017 16:22:24 +0000 (18:22 +0200)]
clk: rockchip: add special approximation to fix up fractional clk's jitter
>From Rockchips fractional divider description:
3.1.9 Fractional divider usage
To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
fractional divider. Generally you must set that denominator is 20 times
larger than numerator to generate precise clock frequency. So the
fractional divider applies only to generate low frequency clock like
I2S, UART.
Therefore add a special approximation function that handles this
special requirement.
Elaine Zhang [Tue, 1 Aug 2017 01:17:03 +0000 (09:17 +0800)]
clk: rockchip: modify rk3128 clk driver to also support rk3126
rk3128 and rk3126 have some gate registers describe differences.
So need to make some distinctions.
The RK3126 and RK3128 Same clock description we move it to
the common clock branches.
And the different clks description use the own clock branches.
Elaine Zhang [Wed, 2 Aug 2017 08:29:48 +0000 (16:29 +0800)]
clk: rockchip: rename the clk id for HCLK_I2S1_2CH
i2s1 has 2 channels but not 8 channels.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
[and the clock id hasn't been used in either clock-driver nor dts,
so is safe to rename] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
On the first revision of the bindings, only the gates + resets were known
in the AO Clock HW, but more registers used to configures AO clock are known
to be spread among the AO register space.
This patch adds a parent node for the entire system control zone for the AO
domain then moves the clock controller as a subnode of the system control
node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Input source 0 of the mmc controllers is not directly xtal, as currently
described in DT. Each controller is fed by a composite clock (the usual
mux, divider and gate). The muxes inputs are the xtal (default) and the
fclk_div clocks. These parents, along with the divider, should be able to
provide the necessary rates for mmc and nand operation.
The input muxes should also be able to take mpll2, mpll3 and gp0_pll but
these are precious clocks, needed for other usage. It is better if the
mmc does not use these them. For this reason, mpll2, mpll3 and gp0_pll is
not listed among the possible parents.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
clk: meson: meson8b: register the built-in reset controller
The clock controller also includes some reset lines. This patch
implements a reset controller to assert and de-assert these resets.
The reset controller itself is registered early (through
CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot
process (to start the secondary CPU cores).
According to the public S805 datasheet there are two more reset bits
in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by
this patch (as these seem to be unused in Amlogic's vendor Linux kernel
sources and their u-boot tree):
- bit 15: GEN_DIV_SOFT_RESET
- bit 14: SOFT_RESET
All information was taken from the public S805 Datasheet and Amlogic's
vendor GPL kernel sources. This patch is based on an earlier version
submitted by Carlo Caione.
Suggested-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Expose all clocks which maybe used as DT bindings
Only clock ids internal the controller remain un-exposed (none on this
particular controller at the moment)
Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
clk: meson: gxbb: fix protection against undefined clks
gxbb clock driver gracefully handles case where the clkid is defined but
the clock hw pointer is not provided, as long as it is not at the end of
the hw_onecell_data array.
This patch ensure that the last entries are defined as well to handle
this particular case.
Fixes: a70c6e06ed7c ("clk: meson: gxbb: protect against holes in the onecell_data array") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
clk: meson: meson8b: fix protection against undefined clks
meson8b clock driver gracefully handles case where the clkid is defined
but the clock hw pointer is not provided, as long as it is not at the end
of the hw_onecell_data array.
This patch ensure that the last entries are defined as well to handle
this particular case.
Fixes: e92f7cca446e ("clk: meson8b: clean up fixed rate clocks") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
This patch utilizes the new PLL clk notifier to gate then ungate the
PLL CPU clock after rate changes. This should prevent any system hangs
resulting from cpufreq changes to the clk.
Tero Kristo [Wed, 2 Aug 2017 18:32:13 +0000 (21:32 +0300)]
clk: keystone: sci-clk: Fix sci_clk_get
Currently a bug in the sci_clk_get implementation causes it to always
return a clock belonging to the last device in the static list of clock
data. This is due to a bug in the init code that causes the array
used by sci_clk_get to only be populated with the clocks for the last
device, as each device overwrites the entire array with its own clocks.
Fix this by calculating the actual number of clocks for the SoC, and
allocating the whole array in one go. Also, we don't need the handle
to the init data array anymore after doing this, instead we can
just compare the dev_id / clk_id against the registered clocks and
use binary search for speed.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Dave Gerlach <d-gerlach@ti.com> Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support") Cc: Nishanth Menon <nm@ti.com> Tested-by: Franklin Cooper <fcooper@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Wed, 2 Aug 2017 16:11:44 +0000 (09:11 -0700)]
Merge tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull one Allwinner clock fix from Chen-Yu Tsai:
One critical clock fix for sun5i (A10s/A13/R8) which enables propagation
of clock rate changes from the "cpu" clock to it's parent PLL clock.
This fixes cpufreq related crashes that have been observed on KernelCI
with the C.H.I.P. and multi_v7_defconfig.
* tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock
N-M factor clock driver is missing a call to ccu_frac_helper_enable()
when fractional mode is used. Additionally, most SoCs require that M
factor must be set to 0 when fractional mode is used.
Without this patch, clock keeps the old value and clk_set_rate() returns
without error.
clk: samsung: exynos5420: The EPLL rate table corrections
This patch fixes values of the EPLL K coefficient and changes
the EPLL output frequency values to match exactly what is
possible to achieve with given M, P, S, K coefficients.
This allows to avoid rounding errors and unexpected frequency
being set with clk_set_rate(), due to recalc_rate returning
different values than the PLL rate specified in the
exynos5420_epll_24mhz_tbl table. E.g. this prevents a case
where two consecutive clk_set_rate() calls with same argument
result in different PLL output frequency.
The PLL output frequencies have been calculated with formula:
dt-bindings: clock: meson8b: describe the embedded reset controller
The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset
lines. These are used for example to boot the secondary CPU cores.
This patch describes the reset controller which is embedded into the
clock controller on these SoCs.
A header file is provided which provides preprocessor macros for each
reset line (to make the .dts files easier to read).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Maxime Ripard [Fri, 21 Jul 2017 16:19:35 +0000 (18:19 +0200)]
clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock
The current CPU clock is missing the option to change the rate of its
parents, leading to improper rates calculated by cpufreq, and eventually
crashes.
Cc: <stable@vger.kernel.org> Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver") Reported-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Rob Herring [Tue, 18 Jul 2017 21:42:52 +0000 (16:42 -0500)]
clk: Convert to using %pOF instead of full_name
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
clk: qoriq: add clock configuration for ls1088a soc
Clock on ls1088a chip takes primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP modules.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Wolfram Sang [Tue, 18 Jul 2017 16:44:07 +0000 (18:44 +0200)]
clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table
Do the checks for accessing the SD divider table only when the rate gets
updated, namely on init and set_rate. In all other cases, reuse the last
value. This simplifies code, runtime load, and error reporting.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>