Stephen Boyd [Thu, 18 Oct 2018 22:41:36 +0000 (15:41 -0700)]
Merge branches 'clk-samsung', 'clk-hisi3670' and 'clk-at91-div-0' into clk-next
- Hisilicon 3670 SoC support
* clk-samsung:
dt-bindings: clock: samsung: Add SPDX license identifiers
clk: samsung: Use clk_hw API for calling clk framework from clk notifiers
clk: samsung: exynos5420: Enable PERIS clocks for suspend
clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420
clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend
clk: samsung: Remove obsolete code for Exynos4412 ISP clocks
clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs
clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume
clk: samsung: exynos5420: Use generic helper for handling suspend/resume
clk: samsung: exynos4: Use generic helper for handling suspend/resume
clk: samsung: Add support for setting registers state before suspend
clk: samsung: exynos5250: Use generic helper for handling suspend/resume
clk: samsung: s5pv210: Use generic helper for handling suspend/resume
clk: samsung: s3c64xx: Use generic helper for handling suspend/resume
clk: samsung: s3c2443: Use generic helper for handling suspend/resume
clk: samsung: s3c2412: Use generic helper for handling suspend/resume
clk: samsung: s3c2410: Use generic helper for handling suspend/resume
clk: samsung: Remove excessive include
* clk-hisi3670:
clk: hisilicon: Add clock driver for Hi3670 SoC
dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk
* clk-at91-div-0:
clk: at91: Fix division by zero in PLL recalc_rate()
Stephen Boyd [Thu, 18 Oct 2018 22:41:21 +0000 (15:41 -0700)]
Merge branch 'clk-ti' into clk-next
* clk-ti:
clk: ti: Prepare for remove of OF node name
clk: Clean up suspend/resume coding style
clk: ti: Add functions to save/restore clk context
clk: clk: Add clk_gate_restore_context function
clk: Add functions to save/restore clock context en-masse
clk: ti: dra7: add new clkctrl data
clk: ti: dra7xx: rename existing clkctrl data as compat data
clk: ti: am43xx: add new clkctrl data for am43xx
clk: ti: am43xx: rename existing clkctrl data as compat data
clk: ti: am33xx: add new clkctrl data for am33xx
clk: ti: am33xx: rename existing clkctrl data as compat data
clk: ti: clkctrl: replace dashes from clkdm name with underscore
clk: ti: clkctrl: support multiple clkctrl nodes under a cm node
dt-bindings: clock: dra7xx: add clkctrl indices for new data layout
dt-bindings: clock: am43xx: add clkctrl indices for new data layout
dt-bindings: clock: am33xx: add clkctrl indices for new data layout
Stephen Boyd [Thu, 18 Oct 2018 22:39:08 +0000 (15:39 -0700)]
Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner', 'clk-mvebu-dup' and 'clk-davinci' into clk-next
- S2RAM support for Marvell mvebu periph clks
* clk-mvebu-periph-pm:
clk: mvebu: armada-37xx-periph: add suspend/resume support
clk: mvebu: armada-37xx-periph: save the IP base address in the driver data
* clk-meson:
clk: meson: meson8b: use the regmap in the internal reset controller
clk: meson: meson8b: register the clock controller early
clk: meson-axg: pcie: drop the mpll3 clock parent
clk: meson: axg: round audio system master clocks down
clk: meson: clk-pll: drop hard-coded rates from pll tables
clk: meson: clk-pll: remove od parameters
clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
clk: meson: clk-pll: add enable bit
* clk-allwinner:
dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
clk: sunxi-ng: a64: Add minimal rate for video PLLs
clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks
clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs
clk: sunxi-ng: nkmp: Add constraint for maximum rate
clk: sunxi-ng: r40: Add max. rate constraint to video PLLs
clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video
clk: sunxi-ng: Add maximum rate constraint to NM PLLs
clk: sunxi-ng: h6: fix PWM gate/reset offset
clk: sunxi-ng: h6: fix bus clocks' divider position
Stephen Boyd [Thu, 18 Oct 2018 22:33:28 +0000 (15:33 -0700)]
Merge branches 'clk-spdx', 'clk-qcom-dfs', 'clk-smp2s11-include', 'clk-qcom-8996-missing' and 'clk-qcom-qspi' into clk-next
- Tag various drivers with SPDX license tags
- Support dynamic frequency switching (DFS) on qcom SDM845 GCC
- Only use s2mps11 dt-binding defines instead of redefining them in the driver
- Add some more missing clks to qcom MSM8996 GCC
- Quad SPI clks on qcom SDM845
* clk-spdx:
clk: mvebu: use SPDX-License-Identifier
clk: renesas: Convert to SPDX identifiers
clk: renesas: use SPDX identifier for Renesas drivers
clk: s2mps11,s3c64xx: Add SPDX license identifiers
clk: max77686: Add SPDX license identifiers
* clk-qcom-dfs:
clk: qcom: Allocate space for NULL terimation in DFS table
clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845
clk: qcom: Add support for RCG to register for DFS
* clk-smp2s11-include:
clk: s2mps11: Use existing defines from bindings for clock IDs
* clk-qcom-8996-missing:
clk: qcom: Add some missing gcc clks for msm8996
* clk-qcom-qspi:
clk: qcom: Add qspi (Quad SPI) clocks for sdm845
clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
Gregory CLEMENT [Wed, 10 Oct 2018 18:18:38 +0000 (20:18 +0200)]
clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in probe
The parent clock is get only to have its name, and then the clock is no
more used, so we can safely free it using clk_put. Furthermore as between
the successful devm_clk_get() and the devm_clk_put() call we don't exit
the probe function in error so I can use non managed version of clk_get()
and clk_put().
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dong Aisheng [Fri, 31 Aug 2018 04:45:54 +0000 (12:45 +0800)]
clk: add new APIs to operate on all available clocks
This patch introduces of_clk_bulk_get_all and clk_bulk_x_all APIs
to users who just want to handle all available clocks from device tree
without need to know the detailed clock information likes clock numbers
and names. This is useful in writing some generic drivers to handle clock
part.
Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Dong Aisheng [Fri, 31 Aug 2018 04:45:53 +0000 (12:45 +0800)]
clk: bulk: add of_clk_bulk_get()
'clock-names' property is optional in DT, so of_clk_bulk_get() is
introduced here to handle this for DT users without 'clock-names'
specified. Later clk_bulk_get_all() will be implemented on top of
it and this API will be kept private until someone proves they need
it because they don't have a struct device pointer.
Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Russell King <linux@arm.linux.org.uk> Reported-by: Shawn Guo <shawnguo@kernel.org> Tested-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Tue, 16 Oct 2018 22:33:01 +0000 (15:33 -0700)]
clk: tegra210: Include size.h for compilation ease
You can't compile this file by itself because it uses SZ_64K from
sizes.h but doesn't include it. Instead it relies on some certain
configuration pulling that in implicitly somewhere else. Just add the
include to make random compile testing easier.
Joseph Lo [Thu, 27 Sep 2018 02:32:03 +0000 (10:32 +0800)]
clk: tegra: Fixes for MBIST work around
Fix some incorrect data in LVL2 offset and bit mask.
Fixes: e403d0057343 ("clk: tegra: MBIST work around for Tegra210") Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Paul Cercueil [Thu, 23 Aug 2018 13:17:41 +0000 (15:17 +0200)]
clk: ingenic: Add proper Kconfig entries
Previously, the CGU code corresponding to the SoC for which we're
compiling the kernel was the only one enabled, which made it impossible
to build one kernel that supports them all.
Now, it is possible to select more than one SoC to support.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Shefali Jain [Wed, 10 Oct 2018 14:51:38 +0000 (20:21 +0530)]
clk: qcom: gcc: Add global clock controller driver for QCS404
Add the clocks supported in global clock controller which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.
Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Co-developed-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
[bamse, vkoul: rebase and tidyup for upstream] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Acked-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Lowercase hex] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Taniya Das [Tue, 25 Sep 2018 17:35:58 +0000 (18:35 +0100)]
clk: qcom: Add Global Clock controller (GCC) driver for SDM660
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[craig: rename parents to fit upstream, and other cleanups] Signed-off-by: Craig Tatlor <ctatlor97@gmail.com> Acked-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Rename gcc_660 to gcc_sdm660 and fix numbering of
defines to avoid duplicates] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Ronald Wahl [Wed, 10 Oct 2018 13:54:54 +0000 (15:54 +0200)]
clk: at91: Fix division by zero in PLL recalc_rate()
Commit a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached MUL
and DIV values") removed a check that prevents a division by zero. This
now causes a stacktrace when booting the kernel on a at91 platform if
the PLL DIV register contains zero. This commit reintroduces this check.
Fixes: a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached...") Cc: <stable@vger.kernel.org> Signed-off-by: Ronald Wahl <rwahl@gmx.de> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Mon, 15 Oct 2018 23:38:33 +0000 (16:38 -0700)]
clk: ti: Prepare for remove of OF node name
Another patch is going to change this code to use %pOFn for DT node
names. Fix up the code to make this easy to pick this side of the merge
instead of fixing it up in a merge commit later.
Cc: Tero Kristo <t-kristo@ti.com> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Mon, 15 Oct 2018 17:01:41 +0000 (10:01 -0700)]
Merge tag 'clk-v4.20-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- consolidation of system suspend related code in Exynos, S5P, S3C SoC clk drivers,
- fixes of system suspend support on Exynos542x (Odroid boards) and Exynos5433 SoC,
- removal of obsoleted Exynos4212 ISP clock definitions,
- correction of Exynos CPU clock implementation,
- addition of SPDX license identifiers.
* tag 'clk-v4.20-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
dt-bindings: clock: samsung: Add SPDX license identifiers
clk: samsung: Use clk_hw API for calling clk framework from clk notifiers
clk: samsung: exynos5420: Enable PERIS clocks for suspend
clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420
clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend
clk: samsung: Remove obsolete code for Exynos4412 ISP clocks
clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs
clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume
clk: samsung: exynos5420: Use generic helper for handling suspend/resume
clk: samsung: exynos4: Use generic helper for handling suspend/resume
clk: samsung: Add support for setting registers state before suspend
clk: samsung: exynos5250: Use generic helper for handling suspend/resume
clk: samsung: s5pv210: Use generic helper for handling suspend/resume
clk: samsung: s3c64xx: Use generic helper for handling suspend/resume
clk: samsung: s3c2443: Use generic helper for handling suspend/resume
clk: samsung: s3c2412: Use generic helper for handling suspend/resume
clk: samsung: s3c2410: Use generic helper for handling suspend/resume
clk: samsung: Remove excessive include
Stephen Boyd [Thu, 11 Oct 2018 16:28:13 +0000 (09:28 -0700)]
clk: Clean up suspend/resume coding style
The normal style is to use 'core' for struct clk_core pointers and to
directly access the core pointer from the clk_hw pointer when we're
within the common clk framework. Update the patches to make it a bit
easier to handle.
Stephen Boyd [Thu, 11 Oct 2018 07:22:55 +0000 (00:22 -0700)]
Merge tag 'clk-ti-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into clk-ti
Pull TI clock driver updates from Tero Kristo:
This tag adds changes for the Texas Instruments clock driver. Included
changes are:
- clkctrl driver changes switching the layout from CM based to clockdomain
based. Needed for ongoing hwmod transition towards sysc driver. Changed
SoCs for this include am3,am4,am5,dra7.
- RTC+DDR sleep mode support code for clock save/restore. The deep sleep
states will wipe the clock register space on the SoC, requiring save/
restore support so that the state can be retained over the sleep state.
* tag 'clk-ti-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
clk: ti: Add functions to save/restore clk context
clk: clk: Add clk_gate_restore_context function
clk: Add functions to save/restore clock context en-masse
clk: ti: dra7: add new clkctrl data
clk: ti: dra7xx: rename existing clkctrl data as compat data
clk: ti: am43xx: add new clkctrl data for am43xx
clk: ti: am43xx: rename existing clkctrl data as compat data
clk: ti: am33xx: add new clkctrl data for am33xx
clk: ti: am33xx: rename existing clkctrl data as compat data
clk: ti: clkctrl: replace dashes from clkdm name with underscore
clk: ti: clkctrl: support multiple clkctrl nodes under a cm node
dt-bindings: clock: dra7xx: add clkctrl indices for new data layout
dt-bindings: clock: am43xx: add clkctrl indices for new data layout
dt-bindings: clock: am33xx: add clkctrl indices for new data layout
clk: ti: fix OF child-node lookup
Arnd Bergmann [Fri, 5 Oct 2018 16:11:15 +0000 (18:11 +0200)]
clk: keystone: add missing MODULE_LICENSE
A randconfig build showed that two clk modules have no license tag:
WARNING: modpost: missing MODULE_LICENSE() in drivers/clk/keystone/gate.o
see include/linux/module.h for more information
WARNING: modpost: missing MODULE_LICENSE() in drivers/clk/keystone/pll.o
see include/linux/module.h for more information
Add the appropriate information from the comment at the start of the
two files.
clk: samsung: Use clk_hw API for calling clk framework from clk notifiers
clk_notifier_register() documentation states, that the provided notifier
callbacks associated with the notifier must not re-enter into the clk
framework by calling any top-level clk APIs. Fix this by replacing
clk_get_rate() calls with clk_hw_get_rate(), which is safe in this
context.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Mon, 24 Sep 2018 11:01:20 +0000 (13:01 +0200)]
clk: samsung: exynos5420: Enable PERIS clocks for suspend
Ensure that clocks for core SoC modules (including TZPC0..9 modules)
are enabled for suspend/resume cycle. This fixes suspend/resume
support on Exynos5422-based Odroid XU3/XU4 boards.
clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420
The bit of GATE_BUS_PERIS1 for CLK_SECKEY is just reserved on
exynos5422/5800, not exynos5420. Define gate clk for exynos5420 to
handle the bit only on exynos5420.
clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs
Before entering system suspend, one has to ensure that some clocks from
TOP, CPIF and PERIC CMUs are enabled. This is needed by the firmware
to properly perform system suspend operation. Instead of adding more and
more clocks with CRITICAL flag, simply enable those clocks directly in
respective CMU registers using 'suspend_regs' feature.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume
SoC clock drivers should suspend after every other drivers in the system,
which are using clocks and resume before them. The last stage for calling
suspend device callbacks is NOIRQ stage and there exists driver, which use
that state (dwmmc-exynos), so Exynos5433 clocks driver should also use it.
During the same stage, clocks driver will be always suspended after its
clients as a direct result of proper device probe order (deferred probe
reorders the suspend call sequence).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
clk: samsung: exynos5420: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
clk: samsung: exynos4: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Handling of PLLs is a bit different in generic code, as they are handled
in the same way as other clock registers. Such approach was already used
on later Exynos SoCs and worked fine. Tests have shown that it works also
on Exynos4 SoCs and significantly simplifies the code.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
clk: samsung: Add support for setting registers state before suspend
Some registers of clock controller have to be set to certain values before
entering system suspend state. Till now drivers did that on their own,
but it will be easier to handle it by generic code and let drivers simply
to provide the list of registers and their state.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
clk: samsung: exynos5250: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
clk: samsung: s5pv210: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
clk: samsung: s3c64xx: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
[snawrocki@kernel.org: Whitespace correction] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
The clock gate restore context function enables or disables
the gate clocks based on the enable_count. This is done in cases
where the clock context is lost and based on the enable_count
the clock either needs to be enabled/disabled.
Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
clk: Add functions to save/restore clock context en-masse
Deep enough power saving mode can result into losing context of the clock
registers also, and they need to be restored once coming back from the power
saving mode. Hence add functions to save/restore clock context.
Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Russ Dill <Russ.Dill@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tero Kristo [Mon, 13 Aug 2018 11:30:49 +0000 (14:30 +0300)]
clk: ti: dra7: add new clkctrl data
The new clkctrl data layout for dra7xx is split based on clockdomain
boundaries. Previously the split was based on CM boundaries. This patch
adds the new data as separate data entity, retaining the compatibility
data also for now. The compatibility data can be removed once no longer
needed.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Mon, 13 Aug 2018 08:11:33 +0000 (11:11 +0300)]
clk: ti: dra7xx: rename existing clkctrl data as compat data
Rename the existing clkctrl data in preparation of upcoming clkdm
based split for it. Once the DT data has transitioned also, the
compat data can be removed.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Mon, 13 Aug 2018 07:48:52 +0000 (10:48 +0300)]
clk: ti: am43xx: add new clkctrl data for am43xx
The new clkctrl data layout for am43xx is split based on clockdomain
boundaries. Previously the split was based on CM boundaries. This patch
adds the new data as separate data entity, retaining the compatibility
data also for now. The compatibility data can be removed once no longer
needed.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Mon, 13 Aug 2018 07:38:40 +0000 (10:38 +0300)]
clk: ti: am43xx: rename existing clkctrl data as compat data
Rename the existing clkctrl data in preparation of upcoming clkdm
based split for it. Once the DT data has transitioned also, the
compat data can be removed.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 10 Aug 2018 15:35:03 +0000 (18:35 +0300)]
clk: ti: am33xx: add new clkctrl data for am33xx
The new clkctrl data layout for am33xx is split based on clockdomain
boundaries. Previously the split was based on CM boundaries. This patch
adds the new data as separate data entity, retaining the compatibility
data also for now. The compatibility data can be removed once no longer
needed.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 10 Aug 2018 15:22:02 +0000 (18:22 +0300)]
clk: ti: am33xx: rename existing clkctrl data as compat data
Rename the existing clkctrl data in preparation of upcoming clkdm
based split for it. Once the DT data has transitioned also, the
compat data can be removed.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Thu, 30 Aug 2018 06:58:31 +0000 (09:58 +0300)]
clk: ti: clkctrl: replace dashes from clkdm name with underscore
The change in the DTS data node naming prevents using underscore
within the node names and force usage of dash instead. On the other
hand, clockdomains use underscore instead of dash, so this must be
replaced within the driver code so that the mapping between the two
can be done properly.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 10 Aug 2018 08:29:09 +0000 (11:29 +0300)]
clk: ti: clkctrl: support multiple clkctrl nodes under a cm node
Currently, only one clkctrl node can be added under a specific CM node
due to limitation with the implementation. Modify the code to pick-up
clockdomain name from the clkctrl node instead of CM node if provided.
Also, add a new flag to the TI clock driver so that both modes can
be supported simultaneously.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 31 Aug 2018 14:44:09 +0000 (17:44 +0300)]
dt-bindings: clock: dra7xx: add clkctrl indices for new data layout
The new data layout will be split based on clockdomain boundaries, instead
of CM boundaries. This introduces a few new clkctrl providers, that have
different indices for the clkctrl data.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 31 Aug 2018 14:42:31 +0000 (17:42 +0300)]
dt-bindings: clock: am43xx: add clkctrl indices for new data layout
The new data layout will be split based on clockdomain boundaries, instead
of CM boundaries. This introduces a few new clkctrl providers, that have
different indices for the clkctrl data.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 31 Aug 2018 14:38:57 +0000 (17:38 +0300)]
dt-bindings: clock: am33xx: add clkctrl indices for new data layout
The new data layout will be split based on clockdomain boundaries, instead
of CM boundaries. This introduces a few new clkctrl providers, that have
different indices for the clkctrl data.
Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
While applying the commit a8309cedcdce ("clk: apn806: Add eMMC clock to
system controller driver"), of_clk_add_provider was added wheres it was
already present in the probe function.
This extraneous call is harmless but not useful so remove it.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Mon, 1 Oct 2018 17:56:17 +0000 (10:56 -0700)]
Merge tag 'clk-renesas-for-v4.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for CMT timer clocks on R-Car V3H
- Add support for SHDI and various timer clocks on R-Car V3M
- Add support for the new RZ/A2 (R7S9210) SoC, including early clock
support for the Renesas CPG/MSSR driver
- Add support for the new RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs
- Convert DT binding includes to SPDX license identifiers
* tag 'clk-renesas-for-v4.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r7s9210: Add SPI clocks
clk: renesas: r7s9210: Move table update to separate function
clk: renesas: r7s9210: Convert some clocks to early
clk: renesas: cpg-mssr: Add early clock support
clk: renesas: r8a77970: Add TPU clock
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0
clk: renesas: cpg-mssr: Add r8a774c0 support
clk: renesas: Add r8a774c0 CPG Core Clock Definitions
clk: renesas: r8a7743: Add r8a7744 support
clk: renesas: Add r8a7744 CPG Core Clock Definitions
dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding
dt-bindings: clock: renesas: Convert to SPDX identifiers
clk: renesas: cpg-mssr: Add R7S9210 support
clk: renesas: r8a77970: Add TMU clocks
clk: renesas: r8a77970: Add CMT clocks
clk: renesas: r9a06g032: Fix UART34567 clock rate
clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI
clk: renesas: r8a77980: Add CMT clocks
Stephen Boyd [Mon, 1 Oct 2018 17:32:32 +0000 (10:32 -0700)]
Merge tag 'meson-clk-4.20-1' of https://github.com/BayLibre/clk-meson into clk-meson
Pull meson clk driver updates from Jerome Brunet:
- clk-pll driver improvements and updates
- add axg audio controller system clocks
- drop mpll3 from the possible pcie clock parent of the axg
- register meson8b clock controller early
* tag 'meson-clk-4.20-1' of https://github.com/BayLibre/clk-meson:
clk: meson: meson8b: use the regmap in the internal reset controller
clk: meson: meson8b: register the clock controller early
clk: meson-axg: pcie: drop the mpll3 clock parent
clk: meson: axg: round audio system master clocks down
clk: meson: clk-pll: drop hard-coded rates from pll tables
clk: meson: clk-pll: remove od parameters
clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
clk: meson: clk-pll: add enable bit
Chris Brandt [Mon, 24 Sep 2018 16:49:35 +0000 (11:49 -0500)]
clk: renesas: cpg-mssr: Add early clock support
Add support for SoCs that need to register core and module clocks early in
order to use OF drivers that exclusively use macros such as
TIMER_OF_DECLARE.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
clk: meson: meson8b: use the regmap in the internal reset controller
For now the reset controller was using raw register access because the
early init did not initialize the regmap. However, now that clocks are
initialized early we can simply use the regmap also for the reset
controller.
No functional changes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
clk: meson: meson8b: register the clock controller early
Until now only the reset controller (part of the clock controller
register space) was registered early in the boot process, while the
clock controller itself was registered later on.
However, some parts of the SoC are initialized early in the boot process,
such as the SRAM and the TWD timer. The bootloader already enables these
clocks so we didn't see any issues so far.
Register the clock controller early so other drivers (such as the SRAM
and TWD timer) can use the clocks early in the boot process.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 1 Aug 2018 14:07:32 +0000 (16:07 +0200)]
clk: meson: axg: round audio system master clocks down
Some of the master clocks provided by the axg audio clock controller are
system clock (spdifin and pdm sysclk). They are used to clock an internal
DSP of the related devices. Having them constantly rounded down instead
of closest is preferable.
Jerome Brunet [Wed, 1 Aug 2018 14:00:53 +0000 (16:00 +0200)]
clk: meson: clk-pll: drop hard-coded rates from pll tables
Putting hard-coded rates inside the parameter tables assumes that
the parent is known and will never change. That's a big assumption
we should not make.
We have everything we need to recalculate the output rate using
the parent rate and the rest of the parameters. Let's do so and
drop the rates from the tables.
Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 1 Aug 2018 14:00:52 +0000 (16:00 +0200)]
clk: meson: clk-pll: remove od parameters
Remove od parameters from pll clocks and add post dividers clocks
instead. Some clock, especially the one which feature several ods,
may provide output between those ods. Also, some drivers, such
as the hdmi driver, may require a more detailed control of the
clock dividers, compared to what CCF would perform automatically.
One added benefit of removing ods is that it also greatly reduce the
size of the rate parameter tables.
In the future, we could possibly take the predivider 'n' out of this
driver as well. To do so, we will need to understand the constraints
for the PLL to lock and whether or not it depends on the input clock
rate.
Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 1 Aug 2018 14:00:51 +0000 (16:00 +0200)]
clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
CLK_GET_RATE_NOCACHE should only be necessary when the registers
controlling the rate of clock may change outside of CCF. On Amlogic,
it should only be the case for the hdmi pll which is directly controlled
by the display driver (WIP to fix this).
The other plls should not require this flag.
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 1 Aug 2018 14:00:50 +0000 (16:00 +0200)]
clk: meson: clk-pll: add enable bit
Add the enable the bit of the pll clocks.
These pll clocks may be disabled but we can't model this as an external
gate since the pll needs to lock when enabled.
Adding this bit allows to drop the poke of the first register of PLL.
This will be useful to model the different components of the pll using
generic clocks elements
Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core
Clock Outputs, as listed in Table 8.2g ("List of Clocks
[RZ/G2E]") of the RZ/G2 Hardware User's Manual.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Chris Brandt [Fri, 7 Sep 2018 16:58:49 +0000 (11:58 -0500)]
clk: renesas: cpg-mssr: Add R7S9210 support
Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module
Standby.
The Module Standby HW in the RZ/A series is very close to R-Car HW, except
for how the registers are laid out.
The MSTP registers are only 8-bits wide, there are no status registers
(MSTPSR), and the register offsets are a little different. Since the RZ/A
hardware manuals refer to these registers as the Standby Control Registers,
we'll use that name to distinguish the RZ/A type from the R-Car type.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Rob Herring <robh@kernel.org> # DT bits Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Phil Edworthy [Fri, 31 Aug 2018 11:26:36 +0000 (12:26 +0100)]
clk: renesas: r9a06g032: Fix UART34567 clock rate
The clock for UARTs 0 through 2 is UART012, the clock for UARTs 3 through
7 is UART34567.
For UART012, we stop the clock driver from changing the clock rate. This
is because the Synopsys UART driver simply sets the reference clock to 16x
the baud rate, but doesn't check if the actual rate is within the required
tolerance. The RZ/N1 clock divider can't provide this (we have to rely on
the UART's internal divider to set the correct clock rate), so you end up
with a clock rate that is way off what you wanted.
In addition, since the clock is shared between multiple UARTs, you don't
want the driver trying to change the clock rate as it may affect the other
UARTs (which may not have been configured yet, so you don't know what baud
rate they will use). Normally, the clock rate is set early on before Linux
to some very high rate that supports all of the clock rates you want.
This change stops the UART34567 clock rate from changing for the same
reasons.
clk: samsung: s3c2443: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
clk: samsung: s3c2412: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
clk: samsung: s3c2410: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>