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4 years agoMerge tag 'mvebu-dt64-5.5-1' of git://git.infradead.org/linux-mvebu into arm/dt
Olof Johansson [Mon, 4 Nov 2019 01:32:25 +0000 (17:32 -0800)]
Merge tag 'mvebu-dt64-5.5-1' of git://git.infradead.org/linux-mvebu into arm/dt

mvebu dt64 for 5.5 (part 1)

 - Add new Marvell CN9130 SoC support (CN9130 is made of one AP807 and
   one internal CP115, similar to the Armada 7K/8K using AP806 and
   CP110).
 - Reorganize EspressoBin device tree to add new variant of the boards
   (Armada 3270 based)
 - Add firmware node for turris Mox (Armada 3720 based)

* tag 'mvebu-dt64-5.5-1' of git://git.infradead.org/linux-mvebu: (23 commits)
  arm64: dts: armada-3720-turris-mox: add firmware node
  arm64: dts: marvell: add ESPRESSObin variants
  arm64: dts: marvell: Add support for Marvell CN9132-DB
  arm64: dts: marvell: Add support for Marvell CN9131-DB
  arm64: dts: marvell: Add support for Marvell CN9130-DB
  arm64: dts: marvell: Add support for Marvell CN9130 SoC support
  arm64: dts: marvell: Add support for CP115
  arm64: dts: marvell: Externalize PCIe macros from CP11x file
  arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file
  arm64: dts: marvell: Prepare the introduction of CP115
  arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment
  arm64: dts: marvell: Add AP807-quad cache description
  arm64: dts: marvell: Add AP806-quad cache description
  arm64: dts: marvell: Add AP806-dual cache description
  arm64: dts: marvell: Add support for AP807/AP807-quad
  dt-bindings: marvell: Declare the CN913x SoC compatibles
  dt-bindings: marvell: Convert the SoC compatibles description to YAML
  arm64: dts: marvell: Move clocks to AP806 specific file
  arm64: dts: marvell: Prepare the introduction of AP807 based SoCs
  MAINTAINERS: Add new Marvell CN9130-based files to track
  ...

Link: https://lore.kernel.org/r/87zhhc3bo6.fsf@FE-laptop
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge tag 'mvebu-dt-5.5-1' of git://git.infradead.org/linux-mvebu into arm/dt
Olof Johansson [Mon, 4 Nov 2019 01:31:40 +0000 (17:31 -0800)]
Merge tag 'mvebu-dt-5.5-1' of git://git.infradead.org/linux-mvebu into arm/dt

mvebu dt for 5.5 (part 1)

 - Enable L2 cache parity and ECC on a Armada XP SoC family and allow
   to use in on the Armada 38x SoCs too.
 - Use correct name for the rs5c372a on synology (Kirkwood based)
 - Rename "sa-sram" node to "sram" on dove

* tag 'mvebu-dt-5.5-1' of git://git.infradead.org/linux-mvebu:
  ARM: dts: armada-xp: add label to sdram-controller node
  ARM: dts: mvebu: add sdram controller node to Armada-38x
  ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg
  ARM: dts: dove: Rename "sa-sram" node to "sram"
  ARM: dts: kirkwood: synology: Fix rs5c372 RTC entry

Link: https://lore.kernel.org/r/8736f44q9l.fsf@FE-laptop
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge tag 'tegra-for-5.5-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git...
Olof Johansson [Mon, 4 Nov 2019 01:31:21 +0000 (17:31 -0800)]
Merge tag 'tegra-for-5.5-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.5-rc1

Adds support for DP and XUSB on various boards, enables SMMU support for
more devices and fixes a couple of DTC warnings and inconsistencies that
are reported at runtime.

These changes along with some of the driver changes in other branches
allow suspend/resume support on Tegra210 devices (e.g. Jetson TX1 and
Jetson Nano).

* tag 'tegra-for-5.5-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits)
  arm64: tegra: Add Jetson Nano SC7 timings
  arm64: tegra: Add Jetson TX1 SC7 timings
  arm64: tegra: Enable wake from deep sleep on RTC alarm
  arm64: tegra: Add PMU on Tegra210
  arm64: tegra: Add blank lines for better readability
  arm64: tegra: Enable DisplayPort on Jetson AGX Xavier
  arm64: tegra: p2888: Rename regulators for consistency
  arm64: tegra: Enable DP support on Jetson TX2
  arm64: tegra: Fix compatible for SOR1
  arm64: tegra: Enable DP support on Jetson Nano
  arm64: tegra: Add SOR0_OUT clock on Tegra210
  arm64: tegra: Assume no CLKREQ presence by default
  arm64: tegra: Enable SMMU for VIC on Tegra186
  arm64: tegra: Enable XUSB host controller on Jetson TX2
  arm64: tegra: Enable SMMU for XUSB host on Tegra186
  arm64: tegra: Enable XUSB pad controller on Jetson TX2
  arm64: tegra: Add ethernet alias on Jetson AGX Xavier
  arm64: tegra: Fix compatible string for EQOS on Tegra194
  arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERM
  arm64: tegra: Fix base address for SOR1 on Tegra194
  ...

Link: https://lore.kernel.org/r/20191102144521.3863321-8-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git...
Olof Johansson [Mon, 4 Nov 2019 01:27:39 +0000 (17:27 -0800)]
Merge tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

ARM: tegra: Device tree changes for v5.5-rc1

Adds support for CPU frequency scaling on Tegra20 and Tegra30, EMC
frequency scaling on Tegra30, SMMU support for VDE on Tegra30, the
STMPE ADC found on Toradex T30 modules as well as fixes for eDP
support on Venice2.

* tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: cardhu-a04: Add CPU Operating Performance Points
  ARM: tegra: cardhu-a04: Set up voltage regulators for DVFS
  ARM: tegra: trimslice: Add CPU Operating Performance Points
  ARM: tegra: paz00: Add CPU Operating Performance Points
  ARM: tegra: paz00: Set up voltage regulators for DVFS
  ARM: tegra: Add CPU Operating Performance Points for Tegra30
  ARM: tegra: Add CPU Operating Performance Points for Tegra20
  ARM: tegra: Add Tegra30 CPU clock
  ARM: tegra: Add Tegra20 CPU clock
  ARM: tegra: Add External Memory Controller node on Tegra30
  ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6
  ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30
  ARM: tegra: Add eDP power supplies on Venice2
  ARM: tegra: Add SOR0_OUT clock on Tegra124
  ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules

Link: https://lore.kernel.org/r/20191102144521.3863321-6-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge tag 'tegra-for-5.5-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel...
Olof Johansson [Mon, 4 Nov 2019 01:19:26 +0000 (17:19 -0800)]
Merge tag 'tegra-for-5.5-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

dt-bindings: Changes for v5.5-rc1

This contains various updates to device tree bindings and includes that
are related to driver changes in other Tegra branches.

* tag 'tegra-for-5.5-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory Controller
  dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller
  dt-bindings: memory: tegra30: Convert to Tegra124 YAML
  dt-bindings: regulator: Document regulators coupling of NVIDIA Tegra20/30 SoCs
  dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT

Link: https://lore.kernel.org/r/20191102144521.3863321-1-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge tag 'sunxi-dt-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git...
Olof Johansson [Mon, 4 Nov 2019 01:07:51 +0000 (17:07 -0800)]
Merge tag 'sunxi-dt-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Our usual bunch of DT patches, with this time mostly:
 - Mali GPU support for the H6
 - Two new crypto drivers enablement
 - A few fixes to our DTs, fixed through the validation effort
 - New boards: NanoPi Duo2

* tag 'sunxi-dt-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (22 commits)
  dt-bindings: arm: sunxi: add FriendlyARM NanoPi Duo2
  ARM: dts: sun8i: add FriendlyARM NanoPi Duo2
  arm64: allwinner: h6: Enable GPU node for Tanix TX6
  arm64: dts: allwinner: bluetooth for Emlid Neutis N5
  ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pins
  ARM: dts: sun9i: a80: Add Security System node
  ARM: dts: sun8i: a83t: Add Security System node
  arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6
  arm64: dts: allwinner: sun50i: Add crypto engine node on H5
  arm64: dts: allwinner: sun50i: Add Crypto Engine node on A64
  ARM: dts: sun8i: H3: Add Crypto Engine node
  ARM: dts: sun8i: R40: add crypto engine node
  dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine
  arm64: dts: allwinner: Add mali GPU supply for H6 boards
  arm64: dts: allwinner: Add ARM Mali GPU node for H6
  ARM: dts: sun8i: a83t: a711: Add touchscreen node
  ARM: dts: sun5i: olinuxino micro: Fix AT24 node name
  ARM: dts: sun9i: Add missing watchdog clocks
  arm64: dts: sun50i: sopine-baseboard: Expose serial1, serial2 and serial3
  arm64: dts: allwinner: orange-pi-3: Enable UART1 / Bluetooth
  ...

Link: https://lore.kernel.org/r/1bf18c83-f41d-4353-9ca2-9585b8693df2.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoARM: dts: atlas7: Fix "debounce-interval" property misspelling
Geert Uytterhoeven [Fri, 1 Nov 2019 16:03:56 +0000 (17:03 +0100)]
ARM: dts: atlas7: Fix "debounce-interval" property misspelling

"debounce_interval" was never supported.

Link: https://lore.kernel.org/r/20191101160356.32034-3-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Barry Song <baohua@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoarm64: dts: lg1313: DT fix s/#interrupts-cells/#interrupt-cells/
Geert Uytterhoeven [Fri, 1 Nov 2019 16:03:55 +0000 (17:03 +0100)]
arm64: dts: lg1313: DT fix s/#interrupts-cells/#interrupt-cells/

The standard DT property is called "#interrupt-cells".

Link: https://lore.kernel.org/r/20191101160356.32034-2-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoarm64: dts: lg1312: DT fix s/#interrupts-cells/#interrupt-cells/
Geert Uytterhoeven [Fri, 1 Nov 2019 16:03:54 +0000 (17:03 +0100)]
arm64: dts: lg1312: DT fix s/#interrupts-cells/#interrupt-cells/

The standard DT property is called "#interrupt-cells".

Link: https://lore.kernel.org/r/20191101160356.32034-1-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge tag 'renesas-dt-bindings-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux...
Olof Johansson [Mon, 4 Nov 2019 01:06:10 +0000 (17:06 -0800)]
Merge tag 'renesas-dt-bindings-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas DT binding updates for v5.5 (take two)

  - JSON schema conversion,
  - Core support for the new R-Car M3-W+ (r8a77961) SoC,
  - Board compatible updates.

* tag 'renesas-dt-bindings-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  dt-bindings: power: rcar-sysc: Document r8a77961 support
  dt-bindings: reset: rcar-rst: Document r8a77961 support
  dt-bindings: arm: renesas: Add Salvator-XS board with R-Car M3-W+
  dt-bindings: arm: renesas: Document R-Car M3-W+ SoC DT bindings
  dt-bindings: arm: renesas: Add R-Car M3-N ULCB with Kingfisher
  dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema

Link: https://lore.kernel.org/r/20191101155842.31467-7-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux...
Olof Johansson [Mon, 4 Nov 2019 01:05:18 +0000 (17:05 -0800)]
Merge tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM64 DT updates for v5.5 (take two)

  - Video-Input and Serial-ATA support on RZ/G2N,
  - Color Management Module support on various R-Car Gen3 SoCs,
  - Initial support for the R-Car M3-W+ (r8a77961) SoC on the
    Salvator-XS board.

* tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+
  arm64: dts: renesas: Add Renesas R8A77961 SoC support
  arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960
  dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
  dt-bindings: power: Add r8a77961 SYSC power domain definitions
  arm64: dts: renesas: r8a774b1: Add SATA controller node
  arm64: dts: renesas: rcar-gen3: Add CMM units
  arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 support

Link: https://lore.kernel.org/r/20191101155842.31467-5-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel...
Olof Johansson [Mon, 4 Nov 2019 01:02:06 +0000 (17:02 -0800)]
Merge tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt

PRM reset control dts changes for v5.5 merge window

This series of changes adds the PRM reset driver nodes for am3/4, omap4/5
and dra7 SoCs. The reset driver changes make it easier to add support for
various accelerators for TI SoCs in a more generic way.

Note that this branch is based on the PRM reset driver changes branch.

* tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: omap5: Add PRM data
  ARM: dts: am43xx: Add PRM data
  ARM: dts: am33xx: Add PRM data
  ARM: dts: omap4: add PRM nodes
  ARM: dts: dra7: add PRM nodes
  soc: ti: omap-prm: add omap5 PRM data
  soc: ti: omap-prm: add am4 PRM data
  soc: ti: omap-prm: add dra7 PRM data
  soc: ti: omap-prm: add data for am33xx
  soc: ti: omap-prm: add omap4 PRM data
  soc: ti: omap-prm: add support for denying idle for reset clockdomain
  soc: ti: omap-prm: poll for reset complete during de-assert
  soc: ti: add initial PRM driver with reset control support
  dt-bindings: omap: add new binding for PRM instances

Link: https://lore.kernel.org/r/pull-1572623173-281197@atomide.com
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoARM: dts: mmp3-dell-ariel: Add a serial point alias
Lubomir Rintel [Thu, 31 Oct 2019 16:34:55 +0000 (17:34 +0100)]
ARM: dts: mmp3-dell-ariel: Add a serial point alias

Make sure UART3, where the console is, is called ttyS2. That is
consistent with the early console.

Link: https://lore.kernel.org/r/20191031163455.1711872-5-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoARM: dts: mmp3-dell-ariel: Add a name to /memory node
Lubomir Rintel [Thu, 31 Oct 2019 16:34:54 +0000 (17:34 +0100)]
ARM: dts: mmp3-dell-ariel: Add a name to /memory node

Ponted out by DTC:

  <stdout>: Warning (unit_address_vs_reg): /memory: node has a reg or ranges
  property, but no unit name

Link: https://lore.kernel.org/r/20191031163455.1711872-4-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoARM: dts: mmp3: Fix /soc/watchdog node name
Lubomir Rintel [Thu, 31 Oct 2019 16:34:53 +0000 (17:34 +0100)]
ARM: dts: mmp3: Fix /soc/watchdog node name

There's a typo there that rightfully upsets DTS:

  <stdout>: Warning (simple_bus_reg): /soc/watchdog@2c000620: simple-bus
  unit address format error, expected "e0000620"

Link: https://lore.kernel.org/r/20191031163455.1711872-3-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoARM: dts: mmp3: Add a name to /clocks node
Lubomir Rintel [Thu, 31 Oct 2019 16:34:52 +0000 (17:34 +0100)]
ARM: dts: mmp3: Add a name to /clocks node

It should have one and DTC is indeed unhappy about its absence:

  <stdout>: Warning (unit_address_vs_reg): /soc/clocks: node has a reg or
  ranges property, but no unit name

Link: https://lore.kernel.org/r/20191031163455.1711872-2-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoARM: dts: Add RDA8810PL GPIO controllers
Manivannan Sadhasivam [Wed, 30 Oct 2019 10:11:54 +0000 (15:41 +0530)]
ARM: dts: Add RDA8810PL GPIO controllers

Add GPIO controllers for RDA8810PL SoC. There are 4 GPIO controllers
in this SoC with maximum of 32 gpios. Except GPIOC, all controllers
are capable of generating edge/level interrupts from first 8 lines.

Link: https://lore.kernel.org/r/20191030101154.6312-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi into arm/dt
Olof Johansson [Mon, 4 Nov 2019 00:56:23 +0000 (16:56 -0800)]
Merge tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi into arm/dt

ARM64: DT: Hisilicon SoCs DT updates for 5.5

- add Mali450 MP4 GPU node in the hi6220 SoC

* tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entry

Link: https://lore.kernel.org/r/5DB95AAB.8060405@hisilicon.com
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel...
Olof Johansson [Mon, 4 Nov 2019 00:54:32 +0000 (16:54 -0800)]
Merge tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into arm/dt

Realtek ARM64 based SoC DT for v5.5

Add RTD1293 and RTD1296 DTs. Add the watchdog for all of RTD129x DTs.
Add reset controllers for RTD129x and start using them for UARTs.

* tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek:
  arm64: dts: realtek: Add RTD129x UART resets
  arm64: dts: realtek: Add RTD129x reset controller nodes
  dt-bindings: reset: Add Realtek RTD1295
  arm64: dts: realtek: Add watchdog node for RTD129x
  arm64: dts: realtek: Add oscillator for RTD129x
  arm64: dts: realtek: Add RTD1296 and Synology DS418
  dt-bindings: arm: realtek: Document RTD1296 and Synology DS418
  arm64: dts: realtek: Add RTD1293 and Synology DS418j
  arm64: dts: realtek: Change dual-license from MIT to BSD
  dt-bindings: arm: realtek: Document RTD1293 and Synology DS418j
  dt-bindings: arm: realtek: Tidy up conversion to json-schema

Link: https://lore.kernel.org/r/20191030041000.31848-2-afaerber@suse.de
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge branch 'for_5.5/keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel...
Olof Johansson [Mon, 4 Nov 2019 00:53:37 +0000 (16:53 -0800)]
Merge branch 'for_5.5/keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/dt

* 'for_5.5/keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
  ARM: configs: keystone: enable cpts
  ARM: dts: k2l-netcp: add cpts refclk_mux node
  ARM: dts: k2hk-netcp: add cpts refclk_mux node
  ARM: dts: k2e-netcp: add cpts refclk_mux node
  ARM: dts: k2e-clocks: add input ext. fixed clocks tsipclka/b
  ARM: dts: keystone-clocks: add input fixed clocks

Link: https://lore.kernel.org/r/1572372856-20598-2-git-send-email-santosh.shilimkar@oracle.com
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agoMerge tag 'socfpga_dts_updates_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel...
Olof Johansson [Sat, 2 Nov 2019 20:34:24 +0000 (13:34 -0700)]
Merge tag 'socfpga_dts_updates_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt

SoCFPGA DTS updates for v5.5
- Arria10
- modify QSPI read-delay property
- Agilex
- Add QSPI support
- Enable USB and LEDs
- Add service layer, fpga manager support
- Stratix10
- Update QSPI reg address

* tag 'socfpga_dts_updates_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: agilex: add service layer, fpga manager and fpga region
  arm64: agilex: enable USB and LEDs on agilex devkit
  arm64: dts: altera: update QSPI reg addresses for Stratix10
  arm64: dts: agilex: add QSPI support for Intel Agilex
  ARM: dts: arria10: Modify QSPI read_delay for Arria10

Link: https://lore.kernel.org/r/20191029143737.24850-1-dinguyen@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
4 years agodt-bindings: arm: sunxi: add FriendlyARM NanoPi Duo2
Karl Palsson [Fri, 1 Nov 2019 20:55:36 +0000 (20:55 +0000)]
dt-bindings: arm: sunxi: add FriendlyARM NanoPi Duo2

Adds bindings for the newly added NanoPi Duo2 board.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoARM: dts: sun8i: add FriendlyARM NanoPi Duo2
Karl Palsson [Fri, 1 Nov 2019 20:55:35 +0000 (20:55 +0000)]
ARM: dts: sun8i: add FriendlyARM NanoPi Duo2

This is an Allwinner H3 based board, with 512MB ram, a USB OTG port,
microsd slot, an onboard AP6212A wifi/bluetooth module, and a CSI
connector.

Full details and schematic available from vendor:
http://wiki.friendlyarm.com/wiki/index.php/NanoPi_Duo2

Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoarm64: allwinner: h6: Enable GPU node for Tanix TX6
Clément Péron [Sat, 2 Nov 2019 12:04:27 +0000 (13:04 +0100)]
arm64: allwinner: h6: Enable GPU node for Tanix TX6

Unlike other H6 boards, Tanix TX6 doesn't have a PMIC so we can enable
the GPU without providing a specific power supply.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoarm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+
Geert Uytterhoeven [Wed, 23 Oct 2019 12:33:40 +0000 (14:33 +0200)]
arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+

Add initial support for the Renesas Salvator-X 2nd version development
board equipped with an R-Car M3-W+ SiP with 8 (2 x 4) GiB of RAM.

The memory map is as follows:
  - Bank0: 4GiB RAM : 0x000048000000 -> 0x000bfffffff
      0x000480000000 -> 0x004ffffffff
  - Bank1: 4GiB RAM : 0x000600000000 -> 0x006ffffffff

Based on a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-10-geert+renesas@glider.be
4 years agoarm64: dts: renesas: Add Renesas R8A77961 SoC support
Geert Uytterhoeven [Wed, 23 Oct 2019 12:33:39 +0000 (14:33 +0200)]
arm64: dts: renesas: Add Renesas R8A77961 SoC support

Add initial support for the Renesas R-Car M3-W+ (R8A77961) SoC.

This includes:
  - Cortex-A57 and Cortex-A53 CPU cores
    (incl. L2 caches and power state definitions),
  - Power Management Unit,
  - PSCI firmware,
  - Pin Function Controller,
  - Clock, Reset, System, and Interrupt Controllers,
  - SCIF2 serial console,
  - Product Register,
  - ARM Architectured Timer,
and various placeholders to allow to use salvator-xs.dtsi.

Based on r8a7796.dtsi.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-9-geert+renesas@glider.be
4 years agoarm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960
Geert Uytterhoeven [Wed, 23 Oct 2019 12:33:38 +0000 (14:33 +0200)]
arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960

CONFIG_ARCH_R8A7796 for R-Car M3-W (R8A77960) will be renamed to
CONFIG_ARCH_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_ARCH_R8A77961.

Relax dependencies by handling both symbols.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-8-geert+renesas@glider.be
4 years agoMerge tag 'renesas-r8a77961-dt-binding-defs-tag' into renesas-arm64-dt-for-v5.5
Geert Uytterhoeven [Fri, 1 Nov 2019 13:03:03 +0000 (14:03 +0100)]
Merge tag 'renesas-r8a77961-dt-binding-defs-tag' into renesas-arm64-dt-for-v5.5

Renesas R-Car M3-W+ DT Binding Definitions

Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.

4 years agodt-bindings: power: rcar-sysc: Document r8a77961 support
Geert Uytterhoeven [Wed, 23 Oct 2019 12:29:10 +0000 (14:29 +0200)]
dt-bindings: power: rcar-sysc: Document r8a77961 support

Add DT binding documentation for the System Controller in the Renesas
R-Car M3-W+ (R8A77961) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20191023122911.12166-5-geert+renesas@glider.be
4 years agodt-bindings: reset: rcar-rst: Document r8a77961 support
Geert Uytterhoeven [Wed, 23 Oct 2019 12:29:09 +0000 (14:29 +0200)]
dt-bindings: reset: rcar-rst: Document r8a77961 support

Add DT binding documentation for the Reset block in the Renesas R-Car
M3-W+ (R8A77961) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20191023122911.12166-4-geert+renesas@glider.be
4 years agodt-bindings: arm: renesas: Add Salvator-XS board with R-Car M3-W+
Geert Uytterhoeven [Wed, 23 Oct 2019 12:29:08 +0000 (14:29 +0200)]
dt-bindings: arm: renesas: Add Salvator-XS board with R-Car M3-W+

Add device tree binding documentation for the Renesas Salvator-XS board
equipped with an R-Car M3-W+ (R8A77961) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Link: https://lore.kernel.org/r/20191023122911.12166-3-geert+renesas@glider.be
4 years agodt-bindings: arm: renesas: Document R-Car M3-W+ SoC DT bindings
Geert Uytterhoeven [Wed, 23 Oct 2019 12:29:07 +0000 (14:29 +0200)]
dt-bindings: arm: renesas: Document R-Car M3-W+ SoC DT bindings

Add device tree binding documentation for the Renesas R-Car M3-W+
(R8A77961) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Link: https://lore.kernel.org/r/20191023122911.12166-2-geert+renesas@glider.be
4 years agodt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
Geert Uytterhoeven [Wed, 23 Oct 2019 12:29:39 +0000 (14:29 +0200)]
dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions

Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
M3-W+ (R8A77961) SoC, as listed in Table 8.2b ("List of Clocks [R-Car
M3-W/R-Car M3-W+]") of the R-Car Series, 3rd Generation Hardware User's
Manual (Rev. 2.00, Jul. 31, 2019).  A gap is added for CSIREF, to
preserve compatibility with the definitions for R-Car M3-W (R8A77960).

Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, SSPSRC, and POST2)
are not included, as they are used as internal clock sources only, and
never referenced from DT.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20191023122941.12342-3-geert+renesas@glider.be
4 years agodt-bindings: power: Add r8a77961 SYSC power domain definitions
Geert Uytterhoeven [Wed, 23 Oct 2019 12:29:11 +0000 (14:29 +0200)]
dt-bindings: power: Add r8a77961 SYSC power domain definitions

Add power domain indices for the R-Car M3-W+ (R8A77961) SoC.

Based on Rev. 2.00 of the R-Car Series, 3rd Generation, Hardware User’s
Manual (Jul. 31, 2019).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Link: https://lore.kernel.org/r/20191023122911.12166-6-geert+renesas@glider.be
4 years agoarm64: dts: allwinner: bluetooth for Emlid Neutis N5
Georgii Staroselskii [Fri, 1 Nov 2019 09:43:33 +0000 (12:43 +0300)]
arm64: dts: allwinner: bluetooth for Emlid Neutis N5

The Emlid Neutis N5 board has AP6212 BT+WiFi chip. This patch is in
line with 8558c6e21ceb ("ARM: dts: sun8i: h3: bluetooth for Banana Pi
M2 Zero board") and other commits that add Bluetooth support for
similar boards.

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pins
Karl Palsson [Thu, 31 Oct 2019 23:11:02 +0000 (23:11 +0000)]
ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pins

uart1 and uart3 had existing pin definitions for the rts/cts pairs.
Add definitions for uart2 as well.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoARM: dts: sun9i: a80: Add Security System node
Corentin Labbe [Fri, 25 Oct 2019 18:51:28 +0000 (20:51 +0200)]
ARM: dts: sun9i: a80: Add Security System node

The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms.
It could be found on Allwinner SoC A80 and A83T

This patch adds it on the Allwinner A80 SoC Device-tree.

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoARM: dts: sun8i: a83t: Add Security System node
Corentin Labbe [Fri, 25 Oct 2019 18:51:27 +0000 (20:51 +0200)]
ARM: dts: sun8i: a83t: Add Security System node

The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms.
It could be found on Allwinner SoC A80 and A83T

This patch adds it on the Allwinner A83T SoC Device-tree.

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoarm64: dts: allwinner: sun50i: Add Crypto Engine node on H6
Corentin Labbe [Wed, 23 Oct 2019 20:05:10 +0000 (22:05 +0200)]
arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6

The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.

This patch enables the Crypto Engine on the Allwinner H6 SoC Device-tree.

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoarm64: dts: allwinner: sun50i: Add crypto engine node on H5
Corentin Labbe [Wed, 23 Oct 2019 20:05:09 +0000 (22:05 +0200)]
arm64: dts: allwinner: sun50i: Add crypto engine node on H5

The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.
It could be found on most Allwinner SoCs.

This patch enables the Crypto Engine on the Allwinner H5 SoC Device-tree.

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoarm64: dts: allwinner: sun50i: Add Crypto Engine node on A64
Corentin Labbe [Wed, 23 Oct 2019 20:05:08 +0000 (22:05 +0200)]
arm64: dts: allwinner: sun50i: Add Crypto Engine node on A64

The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.
It could be found on most Allwinner SoCs.

This patch enables the Crypto Engine on the Allwinner A64 SoC Device-tree.

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoARM: dts: sun8i: H3: Add Crypto Engine node
Corentin Labbe [Wed, 23 Oct 2019 20:05:07 +0000 (22:05 +0200)]
ARM: dts: sun8i: H3: Add Crypto Engine node

The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.
It could be found on most Allwinner SoCs.

This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree.

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoARM: dts: sun8i: R40: add crypto engine node
Corentin Labbe [Wed, 23 Oct 2019 20:05:06 +0000 (22:05 +0200)]
ARM: dts: sun8i: R40: add crypto engine node

The Crypto Engine is a hardware cryptographic offloader that supports
many algorithms.
It could be found on most Allwinner SoCs.

This patch enables the Crypto Engine on the Allwinner R40 SoC Device-tree.

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agodt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine
Corentin Labbe [Wed, 23 Oct 2019 20:05:05 +0000 (22:05 +0200)]
dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine

This patch adds documentation for Device-Tree bindings for the
Crypto Engine cryptographic accelerator driver.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoarm64: dts: allwinner: Add mali GPU supply for H6 boards
Clément Péron [Wed, 30 Oct 2019 15:07:42 +0000 (16:07 +0100)]
arm64: dts: allwinner: Add mali GPU supply for H6 boards

Enable and add supply to the Mali GPU node on all the
H6 boards.

Regarding the datasheet the maximum time for supply to reach
its voltage is 32ms.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoarm64: dts: allwinner: Add ARM Mali GPU node for H6
Clément Péron [Wed, 30 Oct 2019 15:07:41 +0000 (16:07 +0100)]
arm64: dts: allwinner: Add ARM Mali GPU node for H6

Add the mali gpu node to the H6 device-tree.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
4 years agoARM: dts: sun8i: a83t: a711: Add touchscreen node
Mylène Josserand [Tue, 29 Oct 2019 00:58:06 +0000 (01:58 +0100)]
ARM: dts: sun8i: a83t: a711: Add touchscreen node

Enable a FocalTech EDT-FT5x06 Polytouch touchscreen.

Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
4 years agoarm64: tegra: Add Jetson Nano SC7 timings
Sowjanya Komatineni [Fri, 16 Aug 2019 19:42:07 +0000 (12:42 -0700)]
arm64: tegra: Add Jetson Nano SC7 timings

Add platform specific SC7 timing configuration to the Jetson Nano device
tree.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Add Jetson TX1 SC7 timings
Sowjanya Komatineni [Fri, 16 Aug 2019 19:42:06 +0000 (12:42 -0700)]
arm64: tegra: Add Jetson TX1 SC7 timings

Add platform specific SC7 timing configuration to the Jetson TX1 device
tree.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Enable wake from deep sleep on RTC alarm
Sowjanya Komatineni [Fri, 16 Aug 2019 19:42:03 +0000 (12:42 -0700)]
arm64: tegra: Enable wake from deep sleep on RTC alarm

This patch updates device tree for RTC and PMC to allow system wake
from deep sleep on RTC alarm.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Add PMU on Tegra210
Thierry Reding [Tue, 29 Oct 2019 11:25:45 +0000 (12:25 +0100)]
arm64: tegra: Add PMU on Tegra210

The NVIDIA Tegra210 contains an ARM PMU v3 that can be used to gather
statistics about the processors and their memory system. Add a device
tree node so that this functionality can be exposed.

Reported-by: William Cohen <giantklein@gmail.com>
Tested-by: William Cohen <giantklein@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Add blank lines for better readability
Thierry Reding [Tue, 29 Oct 2019 11:20:00 +0000 (12:20 +0100)]
arm64: tegra: Add blank lines for better readability

Separate the individual thermal zones by a blank line for improved
readability.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Enable DisplayPort on Jetson AGX Xavier
Thierry Reding [Thu, 27 Jun 2019 10:23:45 +0000 (12:23 +0200)]
arm64: tegra: Enable DisplayPort on Jetson AGX Xavier

Enable both USB-C/DP ports on Jetson AGX Xavier and wire up the power
supplies for the SORs that drive these outputs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: p2888: Rename regulators for consistency
Thierry Reding [Thu, 27 Jun 2019 10:22:26 +0000 (12:22 +0200)]
arm64: tegra: p2888: Rename regulators for consistency

Some of the PMIC regulators had names that don't match the schematics.
Rename them so that it is easier to cross-reference with the hardware
documentation.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Enable DP support on Jetson TX2
Thierry Reding [Thu, 1 Feb 2018 16:19:09 +0000 (17:19 +0100)]
arm64: tegra: Enable DP support on Jetson TX2

If equipped with an E3320 display module, Jetson TX2 can support
DisplayPort.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Fix compatible for SOR1
Thierry Reding [Mon, 19 Mar 2018 09:29:36 +0000 (10:29 +0100)]
arm64: tegra: Fix compatible for SOR1

It turns out that both SORs on Tegra186 are the same, so there's no need
to distinguish between them in the compatible string.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Enable DP support on Jetson Nano
Thierry Reding [Mon, 24 Jun 2019 13:57:07 +0000 (15:57 +0200)]
arm64: tegra: Enable DP support on Jetson Nano

Add the AVDD_IO_EDP_1V05 and enable the SOR and DPAUX hardware blocks
that are used to drive DisplayPort on Jetson Nano.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Add SOR0_OUT clock on Tegra210
Thierry Reding [Fri, 28 Jun 2019 08:59:19 +0000 (10:59 +0200)]
arm64: tegra: Add SOR0_OUT clock on Tegra210

This clock was not previously used because it is a fixed clock. However,
adding it here allows operating systems to deal with SOR0 the same way
as SOR1.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Assume no CLKREQ presence by default
Vidya Sagar [Sat, 5 Oct 2019 16:42:12 +0000 (22:12 +0530)]
arm64: tegra: Assume no CLKREQ presence by default

Although Tegra194 has support for CLKREQ sideband signal and P2972
has routing of the same till the slot, it is the case most of the time
that the connected device doesn't have CLKREQ support. Hence, it makes
sense to assume that there is no CLKREQ support by default and it can
be enabled on need basis when a card with CLKREQ support is connected.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Enable SMMU for VIC on Tegra186
Thierry Reding [Thu, 24 Jan 2019 18:02:54 +0000 (19:02 +0100)]
arm64: tegra: Enable SMMU for VIC on Tegra186

Enable address translation for VIC via the SMMU on Tegra186.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Enable XUSB host controller on Jetson TX2
Nagarjuna Kristam [Tue, 17 Sep 2019 06:56:45 +0000 (12:26 +0530)]
arm64: tegra: Enable XUSB host controller on Jetson TX2

This enables the use of the USB ports found on the Jetson TX2 for input
or external storage, for example.

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Enable SMMU for XUSB host on Tegra186
Nagarjuna Kristam [Tue, 17 Sep 2019 06:56:44 +0000 (12:26 +0530)]
arm64: tegra: Enable SMMU for XUSB host on Tegra186

Enabling the SMMU for XUSB host allows buffers to be mapped through the
ARM SMMU, which helps protecting the system from rogue memory accesses
by the XUSB host.

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Enable XUSB pad controller on Jetson TX2
Nagarjuna Kristam [Tue, 17 Sep 2019 06:56:43 +0000 (12:26 +0530)]
arm64: tegra: Enable XUSB pad controller on Jetson TX2

The XUSB pad controller is a prerequisite for enabling XUSB support.

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Add ethernet alias on Jetson AGX Xavier
Thierry Reding [Tue, 1 Oct 2019 14:06:12 +0000 (16:06 +0200)]
arm64: tegra: Add ethernet alias on Jetson AGX Xavier

The Tegra194 EQOS controller is used as primary Ethernet interface.
Set the ethernet0 alias to reflect that.

Generic bootloader code can use this to find the primary Ethernet device
and set the MAC address, for example.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Fix compatible string for EQOS on Tegra194
Thierry Reding [Wed, 25 Sep 2019 11:38:51 +0000 (13:38 +0200)]
arm64: tegra: Fix compatible string for EQOS on Tegra194

The EQOS Ethernet controller found on Tegra194 is compatible with its
predecessor or Tegra186. However, it is an established practice to add
a compatible string for the most recent generation of the SoC as well,
just in case some incompatibilities or bugs are later discovered.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERM
Thierry Reding [Thu, 29 Aug 2019 10:56:47 +0000 (12:56 +0200)]
arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERM

For some reason this was never hooked up. Do it now so that over-current
interrupts can be logged.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Fix base address for SOR1 on Tegra194
Thierry Reding [Fri, 26 Jul 2019 10:16:18 +0000 (12:16 +0200)]
arm64: tegra: Fix base address for SOR1 on Tegra194

The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Add unit-address for ACONNECT on Tegra194
Thierry Reding [Fri, 26 Jul 2019 10:16:17 +0000 (12:16 +0200)]
arm64: tegra: Add unit-address for ACONNECT on Tegra194

The ACONNECT complex starts at physical address 0x2900000, so give it a
unit-address to comply with standard naming practices checked for by the
device tree compiler.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Add unit-address for CBB on Tegra194
Thierry Reding [Fri, 26 Jul 2019 10:16:16 +0000 (12:16 +0200)]
arm64: tegra: Add unit-address for CBB on Tegra194

The control back-bone (CBB) starts at physical address 0, so give it a
unit-address to comply with standard naming practices checked for by the
device tree compiler.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Add CPU and cache topology for Tegra194
Thierry Reding [Fri, 20 Sep 2019 14:56:21 +0000 (16:56 +0200)]
arm64: tegra: Add CPU and cache topology for Tegra194

Tegra194 has four CPU clusters, each with their own cache hierarchy.
This patch creates the CPU map for these clusters and adds the second-
and third-level caches and associates them with the CPUs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Fix 'active-low' warning for Jetson Xavier regulator
Jon Hunter [Wed, 25 Sep 2019 14:12:28 +0000 (15:12 +0100)]
arm64: tegra: Fix 'active-low' warning for Jetson Xavier regulator

Commit 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information
in p2972-0000 platform") added regulators for the PCIe slot on the
Jetson Xavier platform. One of these regulators has an active-low enable
and this commit incorrectly added an active-low specifier for the GPIO
which causes the following warning to occur on boot ...

 WARNING KERN regulator@3 GPIO handle specifies active low - ignored

The fixed-regulator binding does not use the active-low flag from the
gpio specifier and purely relies of the presence of the
'enable-active-high' property to determine if it is active high or low
(if this property is omitted). Fix this warning by setting the GPIO
to active-high in the GPIO specifier. Finally, remove the
'enable-active-low' as this is not a valid property.

Fixes: 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information in p2972-0000 platform")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: tegra: Fix 'active-low' warning for Jetson TX1 regulator
Jon Hunter [Wed, 25 Sep 2019 14:12:29 +0000 (15:12 +0100)]
arm64: tegra: Fix 'active-low' warning for Jetson TX1 regulator

Commit 34993594181d ("arm64: tegra: Enable HDMI on Jetson TX1")
added a regulator for HDMI on the Jetson TX1 platform. This regulator
has an active high enable, but the GPIO specifier for enabling the
regulator incorrectly defines it as active-low. This causes the
following warning to occur on boot ...

 WARNING KERN regulator@10 GPIO handle specifies active low - ignored

The fixed-regulator binding does not use the active-low flag from the
gpio specifier and purely relies of the presence of the
'enable-active-high' property to determine if it is active high or low
(if this property is omitted). Fix this warning by setting the GPIO
to active-high in the GPIO specifier which aligns with the presense of
the 'enable-active-high' property.

Fixes: 34993594181d ("arm64: tegra: Enable HDMI on Jetson TX1")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoMerge branch 'for-5.5/dt-bindings'
Thierry Reding [Tue, 29 Oct 2019 19:29:48 +0000 (20:29 +0100)]
Merge branch 'for-5.5/dt-bindings'

4 years agoARM: tegra: cardhu-a04: Add CPU Operating Performance Points
Dmitry Osipenko [Thu, 24 Oct 2019 22:14:16 +0000 (01:14 +0300)]
ARM: tegra: cardhu-a04: Add CPU Operating Performance Points

Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on
Cardhu A04.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: cardhu-a04: Set up voltage regulators for DVFS
Dmitry Osipenko [Thu, 24 Oct 2019 22:14:15 +0000 (01:14 +0300)]
ARM: tegra: cardhu-a04: Set up voltage regulators for DVFS

Set minimum and maximum voltages, and couple CPU/CORE regulators.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: trimslice: Add CPU Operating Performance Points
Dmitry Osipenko [Thu, 24 Oct 2019 22:14:14 +0000 (01:14 +0300)]
ARM: tegra: trimslice: Add CPU Operating Performance Points

Utilize common Tegra20 CPU OPP table. CPU voltage scaling is available
now on TrimSlice.

Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: paz00: Add CPU Operating Performance Points
Dmitry Osipenko [Thu, 24 Oct 2019 22:14:13 +0000 (01:14 +0300)]
ARM: tegra: paz00: Add CPU Operating Performance Points

Utilize common Tegra20 CPU OPP table. CPU DVFS is available now on
AC100.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: paz00: Set up voltage regulators for DVFS
Dmitry Osipenko [Thu, 24 Oct 2019 22:14:12 +0000 (01:14 +0300)]
ARM: tegra: paz00: Set up voltage regulators for DVFS

Set minimum and maximum voltages, and couple CPU/CORE/RTC regulators.

Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: Add CPU Operating Performance Points for Tegra30
Dmitry Osipenko [Thu, 24 Oct 2019 22:14:11 +0000 (01:14 +0300)]
ARM: tegra: Add CPU Operating Performance Points for Tegra30

Operating Point are specified per HW version. The OPP voltages are kept
in a separate DTSI file because some boards may not define CPU regulator
in their device-tree if voltage scaling isn't necessary for them.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: Add CPU Operating Performance Points for Tegra20
Dmitry Osipenko [Thu, 24 Oct 2019 22:14:10 +0000 (01:14 +0300)]
ARM: tegra: Add CPU Operating Performance Points for Tegra20

Operating Point are specified per HW version. The OPP voltages are kept
in a separate DTSI file because some boards may not define CPU regulator
in their device-tree if voltage scaling isn't necessary, like for example
in a case of tegra20-trimslice which is outlet-powered device.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: Add Tegra30 CPU clock
Dmitry Osipenko [Thu, 24 Oct 2019 22:14:09 +0000 (01:14 +0300)]
ARM: tegra: Add Tegra30 CPU clock

All "geared" CPU cores share the same CPU clock.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: Add Tegra20 CPU clock
Dmitry Osipenko [Thu, 24 Oct 2019 22:14:08 +0000 (01:14 +0300)]
ARM: tegra: Add Tegra20 CPU clock

All CPU cores share the same CPU clock.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: Add External Memory Controller node on Tegra30
Dmitry Osipenko [Sun, 11 Aug 2019 21:00:43 +0000 (00:00 +0300)]
ARM: tegra: Add External Memory Controller node on Tegra30

Add External Memory Controller node to the device-tree.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: nyan-big: Add timings for RAM codes 4 and 6
Dmitry Osipenko [Tue, 23 Jul 2019 03:37:44 +0000 (06:37 +0300)]
ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6

Add timings for RAM codes 4 and 6 and a timing for 528mHz of RAM code 1,
which was missed due to the clock driver bug that is fixed now in all of
stable kernels.

Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30
Dmitry Osipenko [Sun, 23 Jun 2019 17:07:24 +0000 (20:07 +0300)]
ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30

Enable IOMMU support for the video decoder.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: Add eDP power supplies on Venice2
Thierry Reding [Thu, 25 Jul 2019 16:22:16 +0000 (18:22 +0200)]
ARM: tegra: Add eDP power supplies on Venice2

The power supplies needed to drive eDP on Venice2 were never hooked up,
so things only worked because those regulators are already enabled by
other devices.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: Add SOR0_OUT clock on Tegra124
Thierry Reding [Wed, 24 Jul 2019 13:47:54 +0000 (15:47 +0200)]
ARM: tegra: Add SOR0_OUT clock on Tegra124

This clock is needed for eDP to properly function, so add it to the SOR
device tree node.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoARM: tegra: Add stmpe-adc DT node to Toradex T30 modules
Philippe Schenker [Wed, 14 Aug 2019 10:53:38 +0000 (10:53 +0000)]
ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules

Add the stmpe-adc DT node as found on Toradex T30 modules

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoMerge branch 'for-5.5/dt-bindings'
Thierry Reding [Tue, 29 Oct 2019 19:28:58 +0000 (20:28 +0100)]
Merge branch 'for-5.5/dt-bindings'

4 years agodt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory Controller
Dmitry Osipenko [Sun, 11 Aug 2019 21:00:39 +0000 (00:00 +0300)]
dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory Controller

Add device-tree binding for NVIDIA Tegra30 External Memory Controller.
The binding is based on the Tegra124 EMC binding since hardware is
similar, although there are couple significant differences.

Note that the memory timing description is given in a platform-specific
form because there is no detailed information on how to convert a
typical-common DDR timing into the register values. The timing format is
borrowed from downstream kernel, hence there is no hurdle in regards to
upstreaming of memory timings for the boards.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agodt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller
Dmitry Osipenko [Sun, 11 Aug 2019 21:00:38 +0000 (00:00 +0300)]
dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller

Add binding for the NVIDIA Tegra30 SoC Memory Controller.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agodt-bindings: memory: tegra30: Convert to Tegra124 YAML
Dmitry Osipenko [Sun, 11 Aug 2019 21:00:37 +0000 (00:00 +0300)]
dt-bindings: memory: tegra30: Convert to Tegra124 YAML

The Tegra30 binding will actually differ from the Tegra124 a tad, in
particular the EMEM configuration description. Hence rename the binding
to Tegra124 during of the conversion to YAML.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agodt-bindings: regulator: Document regulators coupling of NVIDIA Tegra20/30 SoCs
Dmitry Osipenko [Thu, 25 Jul 2019 15:18:30 +0000 (18:18 +0300)]
dt-bindings: regulator: Document regulators coupling of NVIDIA Tegra20/30 SoCs

There is voltage coupling between three regulators on Tegra20 boards and
between two on Tegra30. The voltage coupling is a SoC-level feature and
thus it is mandatory and common for all of the Tegra boards.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agodt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT
Thierry Reding [Tue, 29 Oct 2019 19:14:44 +0000 (20:14 +0100)]
dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT

Tegra186 and later call this clock SOR0_OUT. Rename it on Tegra124 and
Tegra210 to make the names consistent.

Keep the old name for now to keep device trees buildable until they have
all been converted.

Signed-off-by: Thierry Reding <treding@nvidia.com>
4 years agoarm64: dts: realtek: Add RTD129x UART resets
Andreas Färber [Sun, 6 Aug 2017 02:44:59 +0000 (04:44 +0200)]
arm64: dts: realtek: Add RTD129x UART resets

Associate the UART nodes with the corresponding reset controller bits.

Signed-off-by: Andreas Färber <afaerber@suse.de>
4 years agoarm64: dts: realtek: Add RTD129x reset controller nodes
Andreas Färber [Sun, 6 Aug 2017 01:33:39 +0000 (03:33 +0200)]
arm64: dts: realtek: Add RTD129x reset controller nodes

Add nodes for the Realtek RTD1295 reset controllers.

Signed-off-by: Andreas Färber <afaerber@suse.de>
4 years agodt-bindings: reset: Add Realtek RTD1295
Andreas Färber [Tue, 15 Aug 2017 21:50:56 +0000 (23:50 +0200)]
dt-bindings: reset: Add Realtek RTD1295

Add a header with symbolic reset indices for Realtek RTD1295 SoC.
Naming was derived from reset-names in an OEM's Device Tree.

Acked-by: Rob Herring <robh@kernel.org>
[AF: Dropped RTD1295 specific binding definition, updated SPDX]
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
4 years agoarm64: dts: realtek: Add watchdog node for RTD129x
Andreas Färber [Sun, 20 Oct 2019 12:41:21 +0000 (14:41 +0200)]
arm64: dts: realtek: Add watchdog node for RTD129x

Add the watchdog node to the RTD129x Device Tree.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
[AF: Moved from RTD1295 to new RTD129x]
Signed-off-by: Andreas Färber <afaerber@suse.de>
4 years agoarm64: dts: realtek: Add oscillator for RTD129x
Andreas Färber [Sun, 20 Oct 2019 12:41:21 +0000 (14:41 +0200)]
arm64: dts: realtek: Add oscillator for RTD129x

Add 27 MHz oscillator clock node.

Signed-off-by: Andreas Färber <afaerber@suse.de>
4 years agoarm64: dts: realtek: Add RTD1296 and Synology DS418
Andreas Färber [Mon, 16 Oct 2017 01:05:30 +0000 (03:05 +0200)]
arm64: dts: realtek: Add RTD1296 and Synology DS418

Add Device Trees for RTD1296 SoC and Synology DiskStation DS418.

Cc: info@synology.com
Signed-off-by: Andreas Färber <afaerber@suse.de>