This patch adds add DPMCLOCKS table implementation
Rename smu_populate_smc_pptable to smu_populate_smc_tables
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Tue, 30 Jul 2019 03:04:58 +0000 (11:04 +0800)]
drm/amd/powerplay: init smu tables for rn
Initialize smu tables for renoir:
WATERMARKS/DPMCLOCKS/SMU_METRICS
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Tue, 30 Jul 2019 02:50:44 +0000 (10:50 +0800)]
drm/amd/powerplay: add smu tables for rn
add and map smu tables for renoir
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Wed, 21 Aug 2019 21:45:52 +0000 (16:45 -0500)]
drm/amd/powerplay: using valid mapping check for rn
Check whether the message mapping is valid
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Fri, 26 Jul 2019 02:51:32 +0000 (10:51 +0800)]
drm/amd/powerplay: fix checking gfxoff status for rn
For renoir, it should use mmSMUIO_GFX_MISC_CNTL to check
gfxoff status. For the first time to enter gfxoff status,
it maybe takes about one second more. So just set the max
timeout to 5s.
GFXOFF_STATUS(bits 2:1)'s description is below:
0=GFXOFF(default).
1=Transition out of GFX State.
2=Not in GFXOFF.
3=Transition into GFXOFF.
Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Tue, 16 Jul 2019 09:33:47 +0000 (17:33 +0800)]
drm/amdgpu: add and enable gfxoff feature
This patch updates gfxoff feature.
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 8 Aug 2019 20:21:44 +0000 (15:21 -0500)]
drm/amdgpu/powerplay: add Renoir VCN power management
Thus VCN can be powered up for normal operations
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Fri, 16 Aug 2019 22:10:11 +0000 (23:10 +0100)]
drm/amd/display: fix a potential null pointer dereference
Currently the pointer init_data is dereferenced on the assignment
of fw_info before init_data is sanity checked to see if it is null.
Fix te potential null pointer dereference on init_data by only
performing dereference after it is null checked.
Addresses-Coverity: ("Dereference before null check") Fixes: 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Sat, 25 May 2019 12:51:09 +0000 (20:51 +0800)]
drm/amdkfd: Make deallocate_hiq_sdma_mqd static
Fix sparse warning:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.c:1846:6:
warning: symbol 'deallocate_hiq_sdma_mqd' was not declared. Should it be static?
Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 21 Aug 2019 13:00:29 +0000 (21:00 +0800)]
drm/amdgpu/sdma5: fix number of sdma5 trap irq types for navi1x
v2: set num_types based on num_instances
navi1x has 2 sdma engines but commit
"e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma
engines with following logic:
(enable irq for sdma0) * 1 time
(enable irq for sdma1) * 1 time
(disable irq for sdma1) * 6 times
as a result, after gpu reset, interrupt for sdma1 is lost.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Francis [Wed, 19 Jun 2019 18:30:59 +0000 (14:30 -0400)]
drm/amd/display: Enable SST DSC in DM
In create_stream_for_sink, check for SST DP connectors
Parse DSC caps to DC format, then, if DSC is supported,
compute the config
DSC hardware will be programmed by dc_commit_state
Tested-by: Mikita Lipski <Mikita.Lipski@amd.com> Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit fixed an issue with underscan commits not updating all
needed timing values, but through various refactors it is no longer
necessary. It causes corruption on odm combine by
overwriting the halved h_active in the stream timing
Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Re-enable enc2_dp_set_dsc_config. This function caused warnings
due to missing register definitions. With the registers added,
this now works
Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
optc dsc config was causing warnings due to missing register
definitions. With the registers restored, the function can
be re-enabled
The reverted commit also disabled sanity checks and dsc
power gating. The sanity check warnings are not associated
with dsc, and power gating on dsc still has an issue on
non-dsc monitors where the dsc hardware block is never init
and so cannot respond to power gating requests. Therefore,
those are left as is
Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 16 Aug 2019 12:56:35 +0000 (14:56 +0200)]
drm/amdgpu: fix dma_fence_wait without reference
We need to grab a reference to the fence we wait for.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kent Russell [Thu, 22 Aug 2019 12:17:40 +0000 (08:17 -0400)]
drm/powerplay: Fix Vega20 Average Power value v4
The SMU changed reading from CurrSocketPower to AverageSocketPower, so
reflect this accordingly. This fixes the issue where Average Power
Consumption was being reported as 0 from SMU 40.46-onward
v2: Fixed headline prefix
v3: Add check for SMU version for proper compatibility
v4: Style fix
Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank.Min [Wed, 21 Aug 2019 03:05:04 +0000 (11:05 +0800)]
drm/amdgpu: unity mc base address for arcturus
arcturus for sriov would use the unified mc base address
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Frank.Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank.Min [Wed, 21 Aug 2019 09:20:34 +0000 (17:20 +0800)]
drm/amdgpu: disable agp for sriov
Since agp is not used for sriov, just disable it
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Frank.Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdkfd: remove set but not used variable 'pdd'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c: In function restore_process_worker:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c:949:29: warning:
variable pdd set but not used [-Wunused-but-set-variable]
It is not used since
commit 5b87245faf57 ("drm/amdkfd: Simplify kfd2kgd interface")
Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Thu, 27 Jun 2019 07:53:50 +0000 (07:53 +0000)]
drm/amdgpu: remove set but not used variable 'psp_enabled'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/nv.c: In function 'nv_common_early_init':
drivers/gpu/drm/amd/amdgpu/nv.c:471:7: warning:
variable 'psp_enabled' set but not used [-Wunused-but-set-variable]
It's not used since inroduction in
commit c6b6a42175f5 ("drm/amdgpu: add navi10 common ip block (v3)")
Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Fix 32-bit divide error in wait_for_alt_mode
When building arm32 allyesconfig:
ld.lld: error: undefined symbol: __aeabi_uldivmod
>>> referenced by dc_link.c
>>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a
>>> referenced by dc_link.c
>>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a
time_taken_in_ns is of type unsigned long long so we need to use div_u64
to avoid this error.
Fixes: b5b1f4554904 ("drm/amd/display: Enable type C hotplug") Reported-by: Randy Dunlap <rdunlap@infradead.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicolai Hähnle [Tue, 20 Aug 2019 13:39:53 +0000 (15:39 +0200)]
drm/amdgpu: prevent memory leaks in AMDGPU_CS ioctl
Error out if the AMDGPU_CS ioctl is called with multiple SYNCOBJ_OUT and/or
TIMELINE_SIGNAL chunks, since otherwise the last chunk wins while the
allocated array as well as the reference counts of sync objects are leaked.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Lock the CRTC when setting CRC source
[Why]
We need to ensure that we're holding the lock on the CRTC when setting
the CRC source since we're modifying the CRTC state directly.
We also need to wait for any outstanding non-blocking commits to finish
so they aren't reading state that's potentially being modified -
non-blocking commits don't hold the CRTC lock while doing commit tail
work.
[How]
Lock the CRTC using its mutex. While holding the lock check if there's
any commit active on the CRTC - if there is, it's non-blocking and
we should wait until it's finished by waiting for hw_done to be
signaled since that's the last point where we touch CRTC state.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Split out DC programming for CRC capture
[Why]
Calling amdgpu_dm_crtc_set_crc_source in amdgpu_dm directly has the
consequence of adding additional vblank references or starting DPRX
CRC capture more than once without calling stop first.
Vblank references for CRC capture should be managed entirely by opening
and closing the CRC file from userspace.
Stream state also shouldn't be required on the CRC so we can close the
file after the CRTC has been disabled.
[How]
Do DC programming required for configuring CRC capture separately from
setting the source. Whenever we re-enable or reset a CRC this
programming should be reapplied.
CRC vblank reference handling in amdgpu_dm can be entirely dropped after
this.
Stream state also no longer needs to be required since we can just defer
the programming to when the stream is actually enabled.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Use connector list for finding DPRX CRC aux
[Why]
This change is a refactor in preparation for adding locking and removing
the requirement for a stream state on the CRTC for enabling CRC capture
to fix igt@kms_plane_multiple@* warnings.
[How]
We can get the aux by finding the matching connector for the CRTC
with the assumption that we're not doing cloning.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Check return code for CRC drm_crtc_vblank_get
[Why]
The call to drm_crtc_vblank_get can fail if vblank is disabled and
we try to increment the reference.
Since drm_crtc_vblank_get internally drops the reference when it fails
it means the subsequent drm_crtc_vblank_put(...) when closing the file
drops a zero reference.
This was found via igt@kms_plane@pixel-format-pipe-A-planes.
[How]
Check the return code and return it on failure.
We wouldn't have been able to enable CRC reading anyway since vblank
wasn't enabled.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 16 Aug 2019 09:11:46 +0000 (17:11 +0800)]
drm/amd/powerplay: correct SW smu11 thermal range settings
Problems with current settings:
1. The min value was overrided to 0 on Vega20 & Navi10. While
the expected should be -273.15 C.
2. The thermal min/max threshold was output in wrong unit on
Navi10 & Arcturus. As TEMP_RANGE_MIN/MAX is already in
millicelsius. And "*1000" in smu_v11_0_start_thermal_control
makes the output wrongly.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Mon, 19 Aug 2019 15:38:02 +0000 (23:38 +0800)]
drm/amd/powerplay: fix variable type errors in smu_v11_0_setup_pptable
fix size type errors, from uint32_t to uint16_t.
it will cause only initializes the highest 16 bits in
smu_get_atom_data_table function.
bug report:
This fixes the following static checker warning.
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:390 smu_v11_0_setup_pptable()
warn: passing casted pointer '&size' to 'smu_get_atom_data_table()' 32 vs 16.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 16 Aug 2019 07:17:42 +0000 (15:17 +0800)]
drm/amd/powerplay: add smu_smc_read_sensor support for arcturus
the bellow patch refine the sensor read sequence,
but missed to add arcuturs support. (arcuturs_ppt.c)
it will cause some sensor is not supported in arcturus.
drm/amd/powerplay: change smu_read_sensor sequence in smu
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tianci.Yin [Mon, 19 Aug 2019 07:30:22 +0000 (15:30 +0800)]
drm/amdgpu/psp: move TMR to cpu invisible vram region
so that more visible vram can be available for umd.
Reviewed-by: Christian König <christian.koenig@amd.com>. Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Fri, 2 Aug 2019 02:55:50 +0000 (22:55 -0400)]
drm/amdkfd: Fill the name field in node topology with asic name v2
The name field in node topology has not been used. We re-purpose it to
hold the asic name, which can be queried by user space applications
through sysfs.
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Calculate bpc based on max_requested_bpc
[Why]
The only place where state->max_bpc is updated on the connector is
at the start of atomic check during drm_atomic_connector_check. It
isn't updated when adding the connectors to the atomic state after
the fact. It also doesn't necessarily reflect the right value when
called in amdgpu during mode validation outside of atomic check.
This can cause the wrong bpc to be used even if the max_requested_bpc
is the correct value.
[How]
Don't rely on state->max_bpc reflecting the real bpc value and just
do the min(...) based on display info bpc and max_requested_bpc.
Fixes: 01933ba42d3d ("drm/amd/display: Use current connector state if NULL when checking bpc") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 15 Aug 2019 13:27:09 +0000 (08:27 -0500)]
drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possible
We need to set certain power gating flags after we determine
if the firmware version is sufficient to support gfxoff.
Previously we set the pg flags in early init, but we later
we might have disabled gfxoff if the firmware versions didn't
support it. Move adding the additional pg flags after we
determine whether or not to support gfxoff.
Fixes: 005440066f92 ("drm/amdgpu: enable gfxoff again on raven series (v2)") Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Tested-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
dmr/amdgpu: Fix compile error with CONFIG_DRM_AMDGPU_GART_DEBUGFS
Double defintion of 'i'
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Tue, 13 Aug 2019 18:38:03 +0000 (14:38 -0400)]
drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0 for GFX10
We have done this for pre-GFX10 asics, but GFX10 did not pick up the
new change. The below is the commit message for that change.
This is recommended by HW designers. Previously when it was set to 1,
the PDE walk error in VM fault will be treated as
PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT.
As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly.
The above behavior is kind of abnormal. Furthermore, the
PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
and it never made it way to production. Therefore, we should set it to 0.
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Wed, 7 Aug 2019 20:21:09 +0000 (16:21 -0400)]
drm/amdgpu: Add more page fault info printing for GFX10
The printing we did for GFX9 was not propogated to GFX10 somehow, so fix
it now.
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Tue, 13 Aug 2019 18:04:26 +0000 (14:04 -0400)]
drm/amdgpu: Add printing for RW extracted from VM_L2_PROTECTION_FAULT_STATUS
RW is also useful in most cases.
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Thu, 1 Aug 2019 19:24:42 +0000 (14:24 -0500)]
drm/amdkfd/gfx10: Calling amdgpu functions to invalidate TLB
Calling amdgpu function to invalidate TLB, instead of using a
kfd implementation. Delete the kfd local TLB invalidation
implementation.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Thu, 1 Aug 2019 19:55:45 +0000 (14:55 -0500)]
drm/amdgpu: Export function to flush TLB of specific vm hub
This is for kfd to reuse amdgpu TLB invalidation function.
On gfx10, kfd only needs to flush TLB on gfx hub but not
on mm hub. So export a function for KFD flush TLB only on
specific hub.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Li [Tue, 6 Aug 2019 17:50:28 +0000 (13:50 -0400)]
drm/amd/display: Load NV12 SOC BB from firmware
[Why]
Previous SOC bounding box firmware loading logic was for NV10, when we
still had it in firmware. Now that it's brought into driver code, and
NV12 BB is in firmware, this logic needs to be repurposed for NV12.
[How]
Set SOC_BOUNDING_BOX_VALID to false, and add the dcn_2_0_nv12_soc BB
struct. In init_soc_bounding_box, load firmware to nv12 BB instead.
In addition, conditionally update and patch the BB, depending on ASIC
REV.
Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michael Strauss [Fri, 26 Jul 2019 16:04:12 +0000 (12:04 -0400)]
drm/amd/display: Enable MPO with pre-blend color processing (RGB)
[Why]
DCN10 performs color processing before MPC combination, causes color
shift in RGB colorspaces when positive brightness offset is applied
However, YCbCr is still unfixed and remains disabled
[How]
Add layerIndex to dc_plane_state and dc_plane_info structs
Re-enable MPO when brightness is adjusted and colorspace is not YCbCr
Set rear plane's brightness offset to 0 when front plane visible
Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
yanyan kang [Mon, 29 Jul 2019 09:46:44 +0000 (17:46 +0800)]
drm/amd/display: audio cannot switch to internal when display turns off
[why]
disable_az_endpoint has been skipped because
dc->debug.az_endpoint_mute_only = true.
[how]
set dc->debug.az_endpoint_mute_only false when PPLIB’s PME notification function
pointer is not NULL at the dcn10_resource construct function,because right now
SMU/PPLIB and DAL all have the AZ D3 force PME notification implemented. AZ D3 should work.
Signed-off-by: yanyan kang <Yanyan.Kang@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Fri, 26 Jul 2019 18:53:20 +0000 (14:53 -0400)]
drm/amd/display: check hpd before retry verify link cap
[why]
During detection link training if a display is disconnected,
the current code will retry 3 times of link training
on disconnected link before giving up.
[how]
Before each retry check for HPD status, only retry
verify link cap when HPD is still high.
Also put a 10ms delay between each retry to improve
the chance of success.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Mon, 29 Jul 2019 15:59:33 +0000 (11:59 -0400)]
drm/amd/display: enable dcn_mem_pwr as golden setting updates
Enable dcn_mem_pwr as golden setting updates
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: fix dcn20 global sync dml param extraction
Currently the paremeters are extracted as if dml is calculating
using pipes as we pass them in. in reality, dml internally merges
pipes into planes if pipe split is detected.
This change adds reverse logic to dcn20_calculate_dlg_params so
that the global sync parameters can be correctly extracted for
all the pipes when pipe split is enabled.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Thu, 25 Jul 2019 22:46:54 +0000 (18:46 -0400)]
drm/amd/display: Add and refine DSC logs in enable sequence
[why]
Some logs messages were not precise and some new log messages
were needed after "get packed PPS" function was introduced
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Remove redundant definition of dwb_source enums
There are repeated (but guarded) definitions of dwb_src enums. There are
also unused entires. Clean them up.
Signed-off-by: Julian Parkin <julian.parkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Register VUPDATE_NO_LOCK interrupts for DCN2
[Why]
These are needed to send back DRM vblank events in the case where VRR
is on. Without the interrupt enabled we're deferring the events into the
vblank queue and userspace is left waiting forever to get back the
events they need.
Found using igt@kms_vrr - the test fails immediately due to vblank
timeout.
[How]
Register them the same way we're handling it for DCN1.
This fixes igt@kms_vrr for DCN2.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Wed, 24 Jul 2019 22:14:46 +0000 (18:14 -0400)]
drm/amd/display: wake up ogam mem pwr before programming ocsc
[Description]
OGAM_MEM_PWR could stay in light up when driver woke up to update gamma.
either disable MEM_LOW power feature or set to OGAM_bypass could make artificial color distortion goes away.
Easy reproduce after LOW_MEM Power feature enables and resume from S3.
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Julian Parkin <jparkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Thu, 25 Jul 2019 21:27:03 +0000 (17:27 -0400)]
drm/amd/display: Correct DSC PPS log
[why]
A misleading message "Programming PPS" appears before both programming
and "query PPS" functions
[how]
Move the message from "log PPS" function to "program PPS" function
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Tue, 23 Jul 2019 20:38:02 +0000 (16:38 -0400)]
drm/amd/display: Remove 4:2:2 DSC support
[why]
If DSC is available, a higher picture quality is achieved by using
DSC with 4:4:4 format. Using 4:2:2 instead does not offer any benefit
and would only introduce loss of quality. Removing it reduces
maintenance and testing effort.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lewis Huang [Mon, 22 Jul 2019 19:23:32 +0000 (15:23 -0400)]
drm/amd/display: reprogram VM config when system resume
[Why]
The vm config will be clear to 0 when system enter S4. It will
cause hubbub didn't know how to fetch data when system resume.
The flip always pending because earliest_inuse_address and
request_address are different.
[How]
Reprogram VM config when system resume
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Thu, 11 Jul 2019 02:41:51 +0000 (22:41 -0400)]
drm/amd/display: Enable type C hotplug
[Why and How]
We want to change where timing is done for alt mode.
Some of the commented out #ifs are needed for DCN20
so we enable them for that case.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
- Need to change interface function signature / add an enum
to reflect the available register field values
[How]
- Add a new enum and modify existing functions to use it instead
of bool
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: update optc odm interface for more than 2 opps
Current optc odm interface only accepts 2 opps, we need to
expand this to allow 4 to 1 odm combine.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>