From 231d8908a66fa98f09553d31ad8cd5f382b29959 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 31 Jan 2019 11:34:10 +0000 Subject: [PATCH] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices This patch defines OOP tables for all CPUs, similarly to what done by Takeshi Kihara and Yoshihiro Kaneko for the R8A77990. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index f2e390f7f1d5..71ff43e3bb41 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -44,6 +44,27 @@ can_clk: can { clock-frequency = <0>; }; + cluster1_opp: opp_table10 { + compatible = "operating-points-v2"; + opp-shared; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -55,6 +76,8 @@ a53_0: cpu@0 { power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_1: cpu@1 { @@ -64,6 +87,8 @@ a53_1: cpu@1 { power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; L2_CA53: cache-controller-0 { -- 2.45.2