From 3aef46bd5bf24a845e05d2531ed61f53ee8c7797 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 10 Nov 2019 07:30:01 +0100 Subject: [PATCH] media: cedrus: Properly signal size in mode register Mode register also holds information if video width is bigger than 2048 and if it is equal to 4096. Rework cedrus_engine_enable() to properly signal this properties. Signed-off-by: Jernej Skrabec Acked-by: Paul Kocialkowski Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 2 +- drivers/staging/media/sunxi/cedrus/cedrus_h265.c | 2 +- drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 9 +++++++-- drivers/staging/media/sunxi/cedrus/cedrus_hw.h | 2 +- drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c | 2 +- drivers/staging/media/sunxi/cedrus/cedrus_regs.h | 2 ++ 6 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c index 74e4c5e3894e..8a09a08b1af2 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c @@ -485,7 +485,7 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, { struct cedrus_dev *dev = ctx->dev; - cedrus_engine_enable(dev, CEDRUS_CODEC_H264); + cedrus_engine_enable(ctx, CEDRUS_CODEC_H264); cedrus_write(dev, VE_H264_SDROT_CTRL, 0); cedrus_write(dev, VE_H264_EXTRA_BUFFER1, diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c index 9bc921866f70..6945dc74e1d7 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c @@ -276,7 +276,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, } /* Activate H265 engine. */ - cedrus_engine_enable(dev, CEDRUS_CODEC_H265); + cedrus_engine_enable(ctx, CEDRUS_CODEC_H265); /* Source offset and length in bits. */ diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c index 93347d3ba360..daf5f244f93b 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c @@ -30,7 +30,7 @@ #include "cedrus_hw.h" #include "cedrus_regs.h" -int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) +int cedrus_engine_enable(struct cedrus_ctx *ctx, enum cedrus_codec codec) { u32 reg = 0; @@ -58,7 +58,12 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) return -EINVAL; } - cedrus_write(dev, VE_MODE, reg); + if (ctx->src_fmt.width == 4096) + reg |= VE_MODE_PIC_WIDTH_IS_4096; + if (ctx->src_fmt.width > 2048) + reg |= VE_MODE_PIC_WIDTH_MORE_2048; + + cedrus_write(ctx->dev, VE_MODE, reg); return 0; } diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h index 27d0882397aa..604ff932fbf5 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h @@ -16,7 +16,7 @@ #ifndef _CEDRUS_HW_H_ #define _CEDRUS_HW_H_ -int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); +int cedrus_engine_enable(struct cedrus_ctx *ctx, enum cedrus_codec codec); void cedrus_engine_disable(struct cedrus_dev *dev); void cedrus_dst_format_set(struct cedrus_dev *dev, diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c index 13c34927bad5..8bcd6b8f9e2d 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c @@ -96,7 +96,7 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) quantization = run->mpeg2.quantization; /* Activate MPEG engine. */ - cedrus_engine_enable(dev, CEDRUS_CODEC_MPEG2); + cedrus_engine_enable(ctx, CEDRUS_CODEC_MPEG2); /* Set intra quantization matrix. */ diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h index 4275a307d282..ace3d49fcd82 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h @@ -35,6 +35,8 @@ #define VE_MODE 0x00 +#define VE_MODE_PIC_WIDTH_IS_4096 BIT(22) +#define VE_MODE_PIC_WIDTH_MORE_2048 BIT(21) #define VE_MODE_REC_WR_MODE_2MB (0x01 << 20) #define VE_MODE_REC_WR_MODE_1MB (0x00 << 20) #define VE_MODE_DDR_MODE_BW_128 (0x03 << 16) -- 2.45.2