From 4f8449b1baed5c4f6c577f1f5ef6918886583fc5 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 2 Jun 2015 15:37:32 +0200 Subject: [PATCH] ARM: dts: sun8i: Add A33 usb-phy and otg nodes Note these are added to the sun8i-a33.dtsi file rather then to the shared sun8i-a23-a33.dtsi file as both the phy and the otg controller on the a33 are slightly different. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a33.dtsi | 33 ++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 85ee08098b7b..faa7d3c1fcea 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -80,6 +80,39 @@ mbus_clk: clk@01c2015c { clock-output-names = "mbus"; }; }; + + soc@01c00000 { + usb_otg: usb@01c19000 { + compatible = "allwinner,sun8i-a33-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ahb1_gates 24>; + resets = <&ahb1_rst 24>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@01c19400 { + compatible = "allwinner,sun8i-a33-usb-phy"; + reg = <0x01c19400 0x14>, + <0x01c1a800 0x4>; + reg-names = "phy_ctrl", + "pmu1"; + clocks = <&usb_clk 8>, + <&usb_clk 9>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&usb_clk 0>, + <&usb_clk 1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + }; }; &pio { -- 2.45.2