From 5d74e18edd7bdb1fcc35bd115af720ebfb8c5cf0 Mon Sep 17 00:00:00 2001 From: Stanley Chu Date: Mon, 30 Dec 2019 13:32:30 +0800 Subject: [PATCH] scsi: ufs-mediatek: configure and enable clk-gating Enable clk-gating with customized delayed timer value in MediaTek Chipsets. Cc: Alim Akhtar Cc: Avri Altman Cc: Bart Van Assche Cc: Bean Huo Cc: Can Guo Cc: Florian Fainelli Cc: Matthias Brugger Link: https://lore.kernel.org/r/1577683950-1702-7-git-send-email-stanley.chu@mediatek.com Reviewed-by: Alim Akhtar Signed-off-by: Stanley Chu Signed-off-by: Martin K. Petersen --- drivers/scsi/ufs/ufs-mediatek.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c index 1f025723b61b..41f80eeada46 100644 --- a/drivers/scsi/ufs/ufs-mediatek.c +++ b/drivers/scsi/ufs/ufs-mediatek.c @@ -210,6 +210,9 @@ static int ufs_mtk_init(struct ufs_hba *hba) /* Enable runtime autosuspend */ hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; + /* Enable clock-gating */ + hba->caps |= UFSHCD_CAP_CLK_GATING; + /* * ufshcd_vops_init() is invoked after * ufshcd_setup_clock(true) in ufshcd_hba_init() thus @@ -298,6 +301,23 @@ static int ufs_mtk_pre_link(struct ufs_hba *hba) return ret; } +static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba) +{ + unsigned long flags; + u32 ah_ms; + + if (ufshcd_is_clkgating_allowed(hba)) { + if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit) + ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, + hba->ahit); + else + ah_ms = 10; + spin_lock_irqsave(hba->host->host_lock, flags); + hba->clk_gating.delay_ms = ah_ms + 5; + spin_unlock_irqrestore(hba->host->host_lock, flags); + } +} + static int ufs_mtk_post_link(struct ufs_hba *hba) { /* disable device LCC */ @@ -313,6 +333,8 @@ static int ufs_mtk_post_link(struct ufs_hba *hba) FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3)); } + ufs_mtk_setup_clk_gating(hba); + return 0; } -- 2.45.2