From 60d74e011c8e7450846563739a8530f823e5d77a Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Mon, 4 Mar 2019 15:27:46 -0800 Subject: [PATCH] drivers: clk: zynqmp: Allow zero divisor value Zero divider is valid and default for some of ZynqMP clocks. Allow zero divisor when CLK_DIVIDER_ALLOW_ZERO for the clock is set. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Signed-off-by: Stephen Boyd --- drivers/clk/zynqmp/divider.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index a371c66e72ef..e146b6fac6b2 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -76,6 +76,13 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, else value = div >> 16; + if (!value) { + WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), + "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", + clk_name); + return parent_rate; + } + return DIV_ROUND_UP_ULL(parent_rate, value); } -- 2.45.2