From b8cb98cd3e2b600794585958dbea53d433d86736 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Tue, 28 May 2019 13:27:11 +0800 Subject: [PATCH] drm/amdgpu/gfx10: fix programming of SC_HIZ_TILE_FIFO_SIZE field max fifo size is 128 and PA_SC_FIFO_SIZE[20:15]=SC_HIZ_TILE_FIFO_SIZE field is programmed in units of two entries, but 6 bits is insufficient to hold value 128/2 = 64, so set this field as 0 which is interpreted by the hardware as maximum physical fifo size(128). Signed-off-by: Xiaojie Yuan Signed-off-by: Jack Xiao Acked-by: Alex Deucher Reviewed-by: Jack Xiao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 72762de47dc0..0cf7c3faa91f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1103,7 +1103,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.max_hw_contexts = 8; adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; adev->gfx.config.sc_prim_fifo_size_backend = 0x100; - adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x0; adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); break; -- 2.45.2