From cc20028f68e760d6958e892aba1f9bafbce63e22 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 5 Jun 2017 13:22:20 -0300 Subject: [PATCH] ARM: dts: imx6: Fix PCI GPIO reset polarity The imx6 PCI driver ignores the GPIO polarity from 'reset-gpio' and considers that the PCI reset is active low, unless the property 'reset-gpio-active-high' is present. Fix the device tree description by explicitly passing the 'GPIO_ACTIVE_LOW' flag to the 'reset-gpio' property. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-ba16.dtsi | 2 +- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +- arch/arm/boot/dts/imx6q-novena.dts | 2 +- arch/arm/boot/dts/imx6qdl-apf6dev.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 2 +- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index 14fa6b25dc45..5fcb0372d58b 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -321,7 +321,7 @@ rtc@32 { &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; fsl,tx-swing-full = <103>; fsl,tx-swing-low = <103>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index 0c5b2c38214e..33eb7f180995 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -435,7 +435,7 @@ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 8 0>; + reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index c21db67349c4..d83cfb6ec598 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -446,7 +446,7 @@ lvds-channel@0 { &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie_novena>; - reset-gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi index 550e100e85fc..9cd2a7477ed7 100644 --- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi @@ -232,7 +232,7 @@ &ipu1_di0_disp0 { &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 2 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio6 2 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi index ed6a89f724a5..1b1872873207 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi @@ -335,7 +335,7 @@ &gpmi { }; &pcie { - reset-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 6e5cb6a99550..d81b0078a100 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -374,7 +374,7 @@ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 17 0>; + reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index ac1989e5d5ad..c5578d1c1ee4 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -296,7 +296,7 @@ t_lcd: t_lcd_default { &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>; status = "okay"; }; -- 2.45.2