From db4d6d9d80fae312909ce4e21c7299b66e709054 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 4 Oct 2017 17:19:16 +1030 Subject: [PATCH] ARM: dts: aspeed: Correctly order UART nodes Order them all by address. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 48 ++++++++++++------------- arch/arm/boot/dts/aspeed-g5.dtsi | 61 ++++++++++++++++---------------- 2 files changed, 54 insertions(+), 55 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index a549413bda3f..4125e07f22f9 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -183,6 +183,27 @@ timer: timer@1e782000 { clock-names = "PCLK"; }; + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + wdt1: wdt@1e785000 { compatible = "aspeed,ast2400-wdt"; reg = <0x1e785000 0x1c>; @@ -197,11 +218,11 @@ wdt2: wdt@1e785020 { status = "disabled"; }; - uart1: serial@1e783000 { + uart6: serial@1e787000 { compatible = "ns16550a"; - reg = <0x1e783000 0x1000>; + reg = <0x1e787000 0x1000>; reg-shift = <2>; - interrupts = <9>; + interrupts = <10>; clocks = <&clk_uart>; no-loopback-test; status = "disabled"; @@ -237,27 +258,6 @@ uart4: serial@1e78f000 { status = "disabled"; }; - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - current-speed = <38400>; - no-loopback-test; - status = "disabled"; - }; - - uart6: serial@1e787000 { - compatible = "ns16550a"; - reg = <0x1e787000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - i2c: i2c@1e78a000 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index de2dafa71651..61cc2d25143a 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -227,6 +227,26 @@ timer: timer@1e782000 { clock-names = "PCLK"; }; + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; wdt1: wdt@1e785000 { compatible = "aspeed,ast2500-wdt"; @@ -247,16 +267,6 @@ wdt3: wdt@1e785040 { status = "disabled"; }; - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x1000>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - lpc: lpc@1e789000 { compatible = "aspeed,ast2500-lpc", "simple-mfd"; reg = <0x1e789000 0x1000>; @@ -287,6 +297,16 @@ lhc: lhc@20 { }; }; + uart6: serial@1e787000 { + compatible = "ns16550a"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + uart2: serial@1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x1000>; @@ -317,27 +337,6 @@ uart4: serial@1e78f000 { status = "disabled"; }; - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - current-speed = <38400>; - no-loopback-test; - status = "disabled"; - }; - - uart6: serial@1e787000 { - compatible = "ns16550a"; - reg = <0x1e787000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - i2c: i2c@1e78a000 { compatible = "simple-bus"; #address-cells = <1>; -- 2.45.2