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clk: core: introduce clk_hw_set_parent()
2019-08-09 Neil Armstrongclk: core: introduce clk_hw_set_parent()
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: remove clk input helper
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: remove ee input bypass clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: clk-regmap: migrate to new parent description method
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: meson8b: migrate to the new parent description...
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: axg: migrate to the new parent description method
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: gxbb: migrate to the new parent description method
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: g12a: migrate to the new parent description method
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: remove ao input bypass clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: axg-aoclk: migrate to the new parent description...
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: gxbb-aoclk: migrate to the new parent descriptio...
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: g12a-aoclk: migrate to the new parent descriptio...
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-29 Alexandre Mergnatclk: meson: axg-audio: migrate to the new parent description...
[jbrunet@baylibre.com: remove CLK_SET_RATE_PARENT from mst muxes]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-07-25 Alexandre Mergnatclk: meson: g12a: fix hifi typo in mali parent_names
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-06-11 Neil Armstrongclk: meson: g12a: mark fclk_div3 as critical
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-06-11 Neil Armstrongclk: meson: g12a: Add support for G12B CPUB clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-06-11 Jerome BrunetMerge branch 'v5.3/dt' into v5.3/drivers
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2019-06-11 Neil Armstrongdt-bindings: clk: meson: add g12b periph clock controller...
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-06-11 Guillaume La Roqueclk: meson-g12a: add temperature sensor clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [fixed commit description]
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2019-06-11 Jerome BrunetMerge branch 'v5.3/dt' into v5.3/drivers
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2019-06-11 Guillaume La Roquedt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [fixed commit message]
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2019-06-11 Martin Blumenstinglclk: meson: meson8b: add the cts_i958 clock
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-06-11 Martin Blumenstinglclk: meson: meson8b: add the cts_mclk_i958 clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-06-11 Martin Blumenstinglclk: meson: meson8b: add the cts_amclk clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-06-11 Jerome BrunetMerge branch 'v5.3/dt' into v5.3/drivers
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2019-06-11 Martin Blumenstingldt-bindings: clock: meson8b: add the audio clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-05-20 Jerome Brunetclk: meson: g12a: add controller register init
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-05-20 Jerome Brunetclk: meson: eeclk: add init regs
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-05-20 Jerome Brunetclk: meson: g12a: add mpll register init sequences
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-05-20 Jerome Brunetclk: meson: mpll: add init callback and regs
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-05-20 Jerome Brunetclk: meson: axg: spread spectrum is on mpll2
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-05-20 Jerome Brunetclk: meson: gxbb: no spread spectrum on mpll0
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-05-20 Jerome Brunetclk: meson: mpll: properly handle spread spectrum
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-05-20 Martin Blumenstinglclk: meson: meson8b: fix a typo in the VPU parent names...
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2019-05-20 Jerome Brunetclk: meson: fix MPLL 50M binding id typo
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-09-26 Martin Blumenstinglclk: meson: meson8b: use the regmap in the internal...
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-09-26 Martin Blumenstinglclk: meson: meson8b: register the clock controller early
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-09-26 Yixun Lanclk: meson-axg: pcie: drop the mpll3 clock parent
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-09-26 Jerome Brunetclk: meson: axg: round audio system master clocks down
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-09-26 Jerome Brunetclk: meson: clk-pll: drop hard-coded rates from pll tables
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-09-26 Jerome Brunetclk: meson: clk-pll: remove od parameters
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-09-26 Jerome Brunetclk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-09-26 Jerome Brunetclk: meson: clk-pll: add enable bit
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Jerome Brunetclk: meson: add gen_clk
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Jerome Brunetclk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Yixun Lanclk: meson-axg: add clocks required by pcie driver
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Jerome Brunetclk: meson: remove unused clk-audio-divider driver
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Jerome Brunetclk: meson: stop rate propagation for audio clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Jerome Brunetclk: meson: axg: add the audio clock controller driver
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Jerome Brunetclk: meson: add axg audio sclk divider driver
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Jerome BrunetMerge remote-tracking branch 'clk/clk-core-duty-cycle...
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2018-07-09 Jerome Brunetclk: meson: add triple phase clock driver
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Jerome Brunetclk: meson: add clk-phase clock driver
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Jerome BrunetMerge branch 'next/dt' into next/drivers
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2018-07-09 Jerome Brunetclk: meson: clean-up meson clock configuration
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Jerome Brunetclk: meson: remove obsolete register access
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-09 Jerome Brunetclk: meson: expose GEN_CLK clkid
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-07-03 Yixun Lanclk: meson-axg: add pcie and mipi clock bindings
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-06-22 Jerome Brunetdt-bindings: clock: add meson axg audio clock controller...
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-06-21 Jerome Brunetclk: meson: audio-divider is one based
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-06-19 Neil Armstrongclk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-21 Jerome Brunetclk: meson: axg: let mpll clocks round closest
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-21 Jerome Brunetclk: meson: mpll: add round closest support
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-21 Martin Blumenstinglclk: meson: meson8b: mark fclk_div2 gate clocks as...
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-18 Jerome Brunetclk: meson: use SPDX license identifiers consistently
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-15 Yixun Lanclk: meson: drop CLK_SET_RATE_PARENT flag
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-15 Qiufang Daiclk: meson-axg: Add AO Clock and Reset controller driver
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-15 Yixun Lanclk: meson: aoclk: refactor common code into dedicated file
Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-15 Jerome BrunetMerge branch 'next/bindings' into next/drivers
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2018-05-15 Yixun Lanclk: meson: migrate to devm_of_clk_add_hw_provider API
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-15 Maxime Jourdanclk: meson: gxbb: add the video decoder clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-15 Martin Blumenstinglclk: meson: meson8b: add support for the NAND clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-15 Yixun Landt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-05-15 Yixun Landt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-04-25 Maxime Jourdanclk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-04-25 Martin Blumenstingldt-bindings: clock: meson8b: export the NAND clock
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-04-25 Martin Blumenstinglclk: meson: meson8b: fix meson8b_cpu_clk parent clock name
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-04-25 Martin Blumenstinglclk: meson: meson8b: fix meson8b_fclk_div3_div clock name
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-04-25 Yixun Lanclk: meson: drop meson_aoclk_gate_regmap_ops
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-02-12 Jerome Brunetclk: meson: add axg misc bit to the mpll driver
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-02-12 Yixun Lanclk: meson: axg: fix the od shift of the sys_pll
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-02-12 Jerome Brunetclk: meson: axg: add the fractional part of the fixed_pll
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-02-12 Jerome Brunetclk: meson: gxbb: add the fractional part of the fixed_pll
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-02-12 Jerome Brunetclk: meson: fix rate calculation of plls with a fractional part
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-02-12 Jerome Brunetclk: meson: add the gxl hdmi pll
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-02-12 Jerome Brunetclk: meson: add od3 to the pll driver
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-02-12 Jerome Brunetclk: meson: use the frac parameter width instead of a constant
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-02-12 Jerome Brunetclk: meson: remove unnecessary rounding in the pll clock
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-02-12 Jerome Brunetclk: meson: remove useless pll rate params tables
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2018-02-12 Jerome Brunetclk: meson: check pll rate param table before using it
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2017-12-23 Martin Blumenstinglclk: meson: mpll: use 64-bit maths in params_from_rate
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2017-12-14 Qiufang Daiclk: meson-axg: add clock controller drivers
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2017-12-14 Jerome BrunetMerge branch 'next/dt' into next/drivers
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2017-12-14 Qiufang Daiclk: meson-axg: add clocks dt-bindings required header
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2017-12-14 Yixun Landt-bindings: clock: add compatible variant for the Meson-AXG
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2017-12-14 Yixun Lanclk: meson: make the spinlock naming more specific
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2017-12-08 Jerome Brunetclk: meson: gxbb: remove IGNORE_UNUSED from mmc clocks
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2017-11-27 Yixun Lanclk: meson: gxbb: fix wrong clock for SARADC/SANA
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2017-06-16 Jerome Brunetclk: meson: gxbb: add all clk81 parents
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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2017-06-16 Jerome BrunetMerge branch 'next/headers' into next/drivers
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